ISL45042IRZ-TK Intersil, ISL45042IRZ-TK Datasheet
ISL45042IRZ-TK
Specifications of ISL45042IRZ-TK
Related parts for ISL45042IRZ-TK
ISL45042IRZ-TK Summary of contents
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... Pb-Free (RoHS Compliant) Applications • LCD Panels Ordering Information PART NUMBER (Notes ISL45042IRZ NOTES: 1. Add “-T*” suffix for tape and reel. Please refer to reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb- free material sets, molding compounds/die attach materials, and ...
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Pin Descriptions PIN OUT Adjustable Sink Current Output Pin. The current sinks into the OUT pin is equal to the DAC setting times the maximum adjustable sink current divided by 128. See SET pin function in “Pin Descriptions” on page ...
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... Moisture Sensitivity (see Technical Brief TB363) All Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 1 Maximum Junction Temperature (Plastic Package +150°C Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Erase/Write Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10,000 Data Retention years @ +85° 18V 5kΩ 10kΩ 10kΩ; Unless Otherwise Specified. ...
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Electrical Specifications Test Conditions: V Typicals are at T PARAMETER CTL EEPROM Program Voltage CTL CTL EEPROM Programming Signal Time Programming Time SET Voltage Resolution SET Differential Nonlinearity SET Zero-Scale Error SET Full-Scale Error SET Current SET External Resistance AVDD ...
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AVDD ISL45042 I SINK CTL CE OUT SET R SET + - COLUMN DRIVER SINGLE PIXEL IN LCD PANEL FIGURE 1. VCOM ADJUSTMENT IN AN LCD PANEL Application Information The application circuit to adjust the V COM panel is shown ...
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Expected Output Voltage The ISL45042 provides an output sink current, which lowers the voltage on the external voltage divider (V voltage). Equations 1 and 2 can be used to calculate the output current (I ) and output voltage (V OUT ...
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Power Supply Sequence The recommended power supply sequencing is shown in Figure 6. When applying power, VDD should be applied before or at the same time as AVDD. The minimum time for t is 0µs. When removing power, the sequence ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...
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Package Outline Drawing L8.3x3A 8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE Rev 4, 2/10 3.00 6 PIN 1 INDEX AREA (4X) 0.15 TOP VIEW 2X 1.950 PIN #1 1 INDEX AREA 0.30 ± 0.10 2.30 ±0.10 ...