TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

Available stocks

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Manufacturer
Quantity
Price
Part Number:
TX4939XBG-400
Manufacturer:
NSC
Quantity:
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Part Number:
TX4939XBG-400
Manufacturer:
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Quantity:
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Part Number:
TX4939XBG-400
Manufacturer:
XILINX
0
64-Bit TX System RISC
TX49 Family
TX4939
Rev. 3.1

TX4939XBG-400 Summary of contents

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TX System RISC TX49 Family TX4939 Rev. 3.1 ...

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... Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property ...

Page 3

... Thank you for new or continued patronage of TOSHIBA semiconductor products. This is the 2005 edition of the user’s manual for the TX4939 64-bit RISC microprocessor. This databook is written accessible to engineers who may be designing a TOSHIBA microprocessor into their products for the first time. No prior knowledge of this device is assumed. What we offer here is basic information about the microprocessor, a discussion of the application fields in which the microprocessor is utilized, and an overview of design methods ...

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...

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... Pin Multiplex for ATA100-0 (Channel 0) ....................................................................................................... 3-14 3.4.4. Pin Multiplex for ATA100-1 (Channel 1) ....................................................................................................... 3-15 3.4.5. Pin Multiplex for Video port .......................................................................................................................... 3-16 3.4.6. Pin Multiplexing for ISA ................................................................................................................................ 3-17 3.4.7. Pin Multiplexing for PCICLK [4:1] ................................................................................................................. 3-17 CHAPTER 4. BOOT CONFIGURATION ......................................................................................................................... 4-1 4. ............................................................................................................................................. 4-1 OOT ONFIGURATION 4. .................................................................................................................................. 4-2 OOT ONFIGURATION ETAIL CHAPTER 5. CLOCK GENERATORS ............................................................................................................................ 5-1 Rev. 3.1 November 1, 2005 ............................................................................................................................. 1-3 ............................................................................................................................ 2-1 ............................................................................................................... 2-4 EATURES i Toshiba RISC Processor TX4939 ...

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... CHAPTER 7. CONFIGURATION REGISTERS ............................................................................................................... 7-1 7. ............................................................................................................................................ 7-1 ETAILED ESCRIPTION 7.1.1. Detecting G-Bus Timeout ............................................................................................................................... 7-1 7.2. R ............................................................................................................................................................. 7-2 EGISTERS 7.2.1. Chip Configuration Register (CCFG) 7.2.2. Chip Revision ID Register (REVID) 7.2.3. Pin Configuration Register (PCFG) 7.2.4. Timeout Error Access Address Register (TOEA) Rev. 3.1 November 1, 2005 G ) .................................................................................................... 5-13 ENERATOR .......................................................................................................................... 6-2 0x8200 .............................................................................. 6-4 0x8208 0x8220 ...................................................................... 6-5 0xE000.......................................................................................... 7-3 0xE008............................................................................................ 7-7 0xE010 ............................................................................................ 7-8 0xE018.........................................................................7-11 ii Toshiba RISC Processor TX4939 ...

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... IMING IAGRAMS Rev. 3.1 November 1, 2005 0xE020........................................................................................... 7-12 0xE030.................................................................................. 7-16 0xE048 ............................................................................ 7-17 0xE060.......................................................................... 7-18 0xE068 .............................................................................................................. 7-19 0xE070 ............................................................................................................. 7-20 0xE100 ........................................................................................ 7-21 0xE108 ......................................................................................... 7-22 0xE110 ........................................................................................ 7-23 0xE118 ......................................................................................... 7-24 0xE800............................................................................ 8-10 0xE808...........................................................8-11 0xE810 ........................................................................... 8-12 0xE818 ........................................................................... 8-13 0xE8C8 .......................................................................... 8-14 0xE8D0 ........................................................................... 8-15 0xE8A0 ................................................................................... 8-16 0xE8A8...................................................................... 8-18 0xE8B0.................................................................................. 8-19 0xE8C0.................................................................................. 8-20 0xE8B8 ................................................................................ 8-21 0xE900 .......................................................................... 8-22 0xE908 .......................................................................... 8-23 0xE910................................................................. 8-24 0xE918.......................................................................... 8-25 0xE8D8 .................................................................................... 8-27 0xE8E0 .................................................................................... 8-28 0xE8E8............................................................................ 8-28 iii Toshiba RISC Processor TX4939 0xE920 ......................................... 8-26 0xE928 ......................................... 8-27 ...

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... PERATIONS 12.3.1. Video Port DMA Controller ......................................................................................................................... 12-3 12.3.2. 8-bit Parallel port ........................................................................................................................................ 12-4 12.3.3. Serial port................................................................................................................................................... 12-5 12.3.4. Data Format ............................................................................................................................................... 12-6 12.3.5. Transmit Window Option ............................................................................................................................ 12-7 12.3.6. Video Port Controller Registers.................................................................................................................. 12-9 12.3.7. Descriptor Format .................................................................................................................................... 12-14 12.3.8. Big Endian Support .................................................................................................................................. 12-16 Rev. 3.1 November 1, 2005 0x5000 ........................................................ 10-13 0x5010..................................................................... 10-15 0x5018 ....................................................... 10-15 0x5020 ........................................................ 10-16 (RTC).......................................................................................................11-1 ODULE 0xFB00 ....................................................................................11-5 0xFB04..................................................................................................11-6 0xFB08 ....................................................11-6 0xFB0C................................................................................11-6 iv Toshiba RISC Processor TX4939 ...

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... External I/O Device – SRAM Dual Address Transfer................................................................................ 14-37 14.5.2. External I/O Device – SRAM Dual Address Transfer................................................................................ 14-39 14.5.3. External I/O Device (Non-burst) – Memory Dual Address Transfer .......................................................... 14-40 CHAPTER 15. DDR SDRAM CONTROLLER ............................................................................................................... 15-1 15.1. F ........................................................................................................................................................... 15-1 EATURES 15. .................................................................................................................................................... 15-2 EGISTER AP 15.3. DDR SDRAM I .................................................................................................................................... 15-3 NTERFACE 15.3.1. Pin Signals ................................................................................................................................................. 15-3 15.4. R .................................................................................................................................................................. 15-4 EAD 15.4.1. Write........................................................................................................................................................... 15-6 15.5. P ........................................................................................................................................................ 15-8 RECHARGE 15. ..................................................................................................................................................... 15-9 OWER OWN Rev. 3.1 November 1, 2005 Toshiba RISC Processor v TX4939 ...

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... P2G Interrupt Mask Register (P2GMASK) ............................................................................................. 16-43 16.4.21. P2G Current Command Register (P2GCCMD) ...................................................................................... 16-43 16.4.22. PCI Bus Arbiter Request Port Register .................................................................................................. 16-44 16.4.23. PCI Bus Arbiter Configuration Register (PBACFG)................................................................................ 16-46 16.4.24. PCI Bus Arbiter Status Register (PBASTATUS) ..................................................................................... 16-47 Rev. 3.1 November 1, 2005 ............................................................................................................. 15-33 APPING ......................................................................................................................... 15-34 PCI Bus Address Conversion)........................................................................ 16-10 G-Bus Address Conversion) ......................................................................... 16-12 ............................................................................................................... 16-25 0xD00C ............................................................................. 16-31 vi Toshiba RISC Processor TX4939 ...

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... When a read command is issued to the device (transfer start position) ................................................... 17-29 17.5.2. When read command is issued to the device (Transfer End Position) ..................................................... 17-31 17.5.3. When Write Command is issued to the device (Transfer Start Position) .................................................. 17-32 17.5.4. When Write Command is issued to the device (Transfer End Position) ................................................... 17-33 Rev. 3.1 November 1, 2005 ................................................................................................................ 16-84 0xDC ................................................................................................. 16-86 0xDD .............................................................................. 16-86 0xDE ......................................................................... 16-87 0xE0 .............................................................. 16-88 ................................................................................................................. 16-89 ...................................................................................................................... 17-29 vii Toshiba RISC Processor TX4939 ...

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... Transmit FIFO Register 0,1,2,3 ................................................................................................................ 19-24 19.4.9. Receive FIFO Register 0,1,2,3................................................................................................................. 19-25 CHAPTER 20. SPI INTERFACE.................................................................................................................................... 20-1 20.1. F ........................................................................................................................................................... 20-1 EATURES 20.2. B .................................................................................................................................................. 20-2 LOCK DIAGRAM 20.3. O .................................................................................................................................. 20-3 PERATIONAL DESCRIPTION 20.3.1. Operation modes ....................................................................................................................................... 20-3 20.3.2. Transmitter/Receiver .................................................................................................................................. 20-3 20.3.3. Baud Rate Generator ................................................................................................................................. 20-4 20.3.4. Transfer format........................................................................................................................................... 20-5 20.3.5. Interframe Delay Time Counter .................................................................................................................. 20-6 20.3.6. Buffer configuration .................................................................................................................................... 20-7 20.3.7. SPI system errors....................................................................................................................................... 20-7 20.3.8. Interrupts.................................................................................................................................................... 20-7 Rev. 3.1 November 1, 2005 . V ) ...................................................................................... 17-37 PEC ALUES viii Toshiba RISC Processor TX4939 ...

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... I2S Interrupt Control Register (I2SICTRL) 23.4.5. I2S Clock Option Register (I2SCOR) 23. ........................................................................................................................................... 23-17 NTERFACE IGNALS CHAPTER 24. ACLINK CONTROLLER ....................................................................................................................... 24-1 24.1. F ........................................................................................................................................................... 24-1 EATURES 24.2. C .................................................................................................................................................. 24-2 ONFIGURATION Rev. 3.1 November 1, 2005 0xF800................................................................................... 20-9 0xF804 ......................................................................................... 20-10 0xF808 ..........................................................................................20-11 0xF80C ......................................................................... 20-12 0xF814 ................................................................................................ 20-13 0xF818 ................................................................................................. 20-14 0xFC00................................................................................ 21-4 0xF900 .................................................................. 22-3 0xF904 .......................................................................... 22-4 0xF908.......................................................................................... 22-4 0xF90C......................................................................................... 22-5 0xF920........................................................................................... 22-6 0xFA00 .......................................................................23-11 0xFA04 .............................................................................. 23-12 0xFA08............................................................................ 23-14 0xFA0C.................................................................................. 23-15 ix Toshiba RISC Processor TX4939 ...

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... Example 3 ................................................................................................................................................ 26-14 26.6.4. Example 4 ................................................................................................................................................ 26-15 26.6.5. Example 5 ................................................................................................................................................ 26-16 26. (RNG) E ANDOM UMBER ENERATOR Rev. 3.1 November 1, 2005 0xF700 ............................................................................................ 24-17 0xF704 ........................................................................................... 24-21 0xF708 .............................................................................. 24-24 0xF710 ........................................................................................... 24-25 0xF714................................................................................ 24-27 0xF718 .......................................................................................... 24-27 0xF71C......................................................................................... 24-27 0xF720 ................................................................................................. 24-28 0xF740 .................................................................................................... 24-29 0xF744 ................................................................................................. 24-30 0xF748................................................................................................ 24-31 0xF74C .............................................................................................. 24-33 0xF750............................................................................................... 24-35 0xF780.................................................................................. 24-37 0xF784.............................................................................. 24-38 0xF7A0 0xF7A4 ........................................................................................... 24-39 0xF7A4 0xF7AC 0xF7B8 ...................................................................................... 24-40 0xF7B0................................................................................ 24-41 0xF7BC .................................................................................... 24-42 0xF7FC............................................................................................... 24-43 0x6000........................................................................................... 25-3 ........................................................................................................................ 26-2 . ............................................................................................... 26-13 .................................................................................................... 26-17 NGINE x Toshiba RISC Processor TX4939 ...

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... DDR SDRAM Interface AC Characteristics ................................................................................................ 28-5 28.4.4. External Bus Interface AC Characteristics ............................................................................................... 28-10 28.4.5. PCI Interface AC Characteristics...............................................................................................................28-11 28.4.6. AC-link Interface AC characteristics ......................................................................................................... 28-13 28.4.7. SPI AC characteristics ............................................................................................................................. 28-14 28.4.8. AC characteristics of ATA Interface .......................................................................................................... 28-15 28.4.9. Ethernet Interface (RMII) AC characteristics ............................................................................................ 28-20 28.4.10. AC Characteristics of Video Port ............................................................................................................ 28-22 CHAPTER 29. PACKAGE OUTER APPEARANCE...................................................................................................... 29-1 29. .............................................................................................................................................. 29-1 ACKAGE RAWING 29. ECOMMENDED OTHERBOARD Rev. 3.1 November 1, 2005 ...................................................................................................................... 27-8 ........................................................................................................................... 27-8 ............................................................................................................... 28-1 ........................................................................................................... 29-2 OOTPRINT xi Toshiba RISC Processor TX4939 ...

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... Figure 8-20 Interrupt Request Internal Interrupt Mask Register............................................................................. 8-26 Figure 8-21 Interrupt Request External Interrupt Mask Register ........................................................................... 8-27 Figure 8-22 Interrupt Debug Register 0 ................................................................................................................. 8-27 Figure 8-23 Interrupt Debug Register 1 ................................................................................................................. 8-28 Figure 8-24 Interrupt Debug Enable Register ........................................................................................................ 8-28 Figure 9-1 External Circuit for External Bus Interface for 8/16-bit mode.................................................................. 9-1 Rev. 3.1 November 1, 2005 Toshiba RISC Processor xii TX4939 ...

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... Figure 12-1 Block Diagram of Video Port Controller.............................................................................................. 12-2 Figure 12-2 ITU.BT656 (CCIR656) Digital Video Timing ....................................................................................... 12-4 Figure 12-3 Transmission format with 188 Byte packets (VDVLD = 1) .................................................................. 12-4 Figure 12-4 Transmission format with 204 Byte packets ....................................................................................... 12-4 Figure 12-5 Transmission format with RS-coded packets (204 Bytes, VDVLD = 1) .............................................. 12-4 Rev. 3.1 November 1, 2005 Toshiba RISC Processor xiii TX4939 ...

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... Figure 15-13 Controller Memory Map: Maximum .............................................................................................. 15-33 Figure 15-14 Alternate Memory Map .................................................................................................................. 15-33 Figure 16-1 PCI Controller Block Diagram ........................................................................................................... 16-3 Figure 16-2 PCI BOOT default mapping............................................................................................................... 16-5 Figure 16-3 Block Diagram of Sample PCI Adapter............................................................................................... 16-6 Figure 16-4 Register Map (Host Mode) ................................................................................................................ 16-7 Figure 16-5 Register Map (Satellite Mode) ........................................................................................................... 16-7 Rev. 3.1 November 1, 2005 Toshiba RISC Processor xiv TX4939 ...

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... Figure 16-63 G2P Special Cycle Data Register.................................................................................................. 16-72 Figure 16-64 ID Register ..................................................................................................................................... 16-73 Figure 16-65 Class Code/Revision ID Register ................................................................................................... 16-73 Figure 16-66 Sub System ID Register ................................................................................................................. 16-74 Figure 16-67 PCI Configuration Register 2.......................................................................................................... 16-74 Figure 16-68 PDMAC Chain Address Register................................................................................................... 16-75 Figure 16-69 G-Bus Address Register................................................................................................................ 16-76 Figure 16-70 PCI Bus Address Register ............................................................................................................. 16-77 Figure 16-71 Count Register .............................................................................................................................. 16-78 Rev. 3.1 November 1, 2005 Toshiba RISC Processor xv TX4939 ...

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... Figure 18-22 PCI Status Register ....................................................................................................................... 18-40 Figure 18-23 Class Code Register ..................................................................................................................... 18-41 Figure 18-24 PCI Control Register ..................................................................................................................... 18-42 Figure 18-25 I/O Base Address Register ............................................................................................................ 18-43 Figure 18-26 Memory Base Address Register .................................................................................................... 18-43 Figure 18-27 Subsystem Vendor ID Number Register........................................................................................ 18-44 Figure 18-28 Subsystem ID Register.................................................................................................................. 18-44 Figure 18-29 PCI Function Pointer Register ....................................................................................................... 18-45 Rev. 3.1 November 1, 2005 Toshiba RISC Processor xvi TX4939 ...

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... Figure 22-4 Internal structure I2C.......................................................................................................................... 22-9 Figure 22-5 Control Flow ......................................................................................................................................22-11 Figure 22-6 Bit Command Control ....................................................................................................................... 22-12 Figure 22-7 Byte Mode ........................................................................................................................................ 22-13 Figure 22-8 Byte Mode ........................................................................................................................................ 22-14 Figure 23-1 the block diagram of the I2SC Interface module. ............................................................................... 23-1 Figure 23-2 the block diagram for I2S clock diagram. ........................................................................................... 23-2 2 Figure 23 Interface........................................................................................................................................ 23-3 Rev. 3.1 November 1, 2005 Toshiba RISC Processor xvii TX4939 ...

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... Figure 28-18 Ethernet Interface Signal Reception............................................................................................... 28-20 Figure 28-19 Ethernet Interface Signal Transmission.......................................................................................... 28-20 Figure 28-20 Ethernet Interface Management Signal Control ............................................................................. 28-21 Figure 28-21 Video Port Transport data input...................................................................................................... 28-22 Figure 28-22 Video port Transport data output .................................................................................................... 28-22 Figure 29-1 Recommended Footprint for heat disspation...................................................................................... 29-2 Rev. 3.1 November 1, 2005 Toshiba RISC Processor xviii TX4939 ...

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... Table 6-31 Internal Registers for I2C Controller..................................................................................................... 6-27 Table 6-32 Internal Registers for I2S Controller ..................................................................................................... 6-27 Table 6-33 Internal Registers for RTC Controller ................................................................................................... 6-27 Table 6-34 Internal Register for CIR Controller ...................................................................................................... 6-27 Table 7-1 Configuration Register Mapping............................................................................................................... 7-2 Table 7-2 Chip Configuration Register ..................................................................................................................... 7-4 Table 7-3 Chip Revision ID Register ........................................................................................................................ 7-7 Rev. 3.1 November 1, 2005 Toshiba RISC Processor xix TX4939 ...

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... Table 11-4 Control IO ports.....................................................................................................................................11-5 Table 11-5 RTCCTL Command Code .....................................................................................................................11-5 Table 11-6 Bit Field Definitions ...............................................................................................................................11-8 Table 12-1 VPR Registers ..................................................................................................................................... 12-9 Table 12-2 Control and Status Register (CSR) .................................................................................................... 12-10 Table 12-3 ControlA Register (CtrlA) ....................................................................................................................12-11 Table 12-4 ControlB Register (CtrlB) ................................................................................................................... 12-12 Table 12-5 Initial Descriptor Pointer Register (IDESPtr) ...................................................................................... 12-12 Rev. 3.1 November 1, 2005 Toshiba RISC Processor xx TX4939 ...

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... Table 16-21 P2G I/O Space PCI Base Address Register.................................................................................... 16-34 Table 16-22 Subsystem ID Register ................................................................................................................... 16-35 Table 16-23 Capabilities Pointer Register........................................................................................................... 16-35 Table 16-24 PCI Configuration 2 Register .......................................................................................................... 16-36 Table 16-25 G2P Timeout Count Register .......................................................................................................... 16-37 Table 16-26 G2P Status Register ....................................................................................................................... 16-37 Table 16-27 G2P Interrupt Mask Register........................................................................................................... 16-38 Table 16-28 Satellite Mode PCI Status Register .................................................................................................. 16-39 Rev. 3.1 November 1, 2005 Toshiba RISC Processor xxi TX4939 ...

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... Table 17-6 ATAPI Packet Command Register ..................................................................................................... 17-21 Table 17-7 ATA Device Timing Error Register ...................................................................................................... 17-22 Table 17-8 Packet Transfer Control Register ....................................................................................................... 17-23 Table 17-9 PIO Transfer Timing .......................................................................................................................... 17-26 Table 17-10 Multiword DMA Transfer Timing ...................................................................................................... 17-28 Table 17-11 Timing Parameters when Ultra DMA Transfer Starts ....................................................................... 17-30 Rev. 3.1 November 1, 2005 Toshiba RISC Processor xxii TX4939 ...

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... Table 24-8 Transmission FIFO Depth ................................................................................................................. 24-13 Table 24-9 DMA Completion Status Determination............................................................................................. 24-13 Table 24-10 ACLC Registers .............................................................................................................................. 24-16 Table 24-11 ACCTLEN Register .......................................................................................................................... 24-17 Table 24-12 ACCTLDIS Register ......................................................................................................................... 24-21 Table 24-13 ACREGACC..................................................................................................................................... 24-24 Table 24-14 ACINTSTS Register ......................................................................................................................... 24-25 Table 24-15 ACSEMAPH Register....................................................................................................................... 24-28 Table 24-16 ACGPIDAT Register........................................................................................................................ 24-29 Table 24-17 ACGPODAT Register ....................................................................................................................... 24-30 Table 24-18 ACSLTEN Register .......................................................................................................................... 24-31 Rev. 3.1 November 1, 2005 Toshiba RISC Processor xxiii TX4939 ...

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... Table 26-24 RNG Output Register 2 (ROR2)....................................................................................................... 26-18 Table 26-25 RNG Output Register 3 (ROR3)....................................................................................................... 26-18 Table 27-1 EJTAG Interface Function and Operation Code.................................................................................. 27-1 Table 27-2 Bit Configuration of JTAG Instruction Register.................................................................................... 27-3 Table 27-3 JTAG Interface .................................................................................................................................... 27-5 Table 27-4 Instruction ........................................................................................................................................... 27-6 Table 27-5 Register Map ...................................................................................................................................... 27-7 Table 29-1 Thermal Resistance of Via and Vias .................................................................................................... 29-2 Rev. 3.1 November 1, 2005 Toshiba RISC Processor xxiv TX4939 ...

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Handling Precautions ...

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...

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... Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or damage to property. ...

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... Using Toshiba Semiconductors Safely 1-2 ...

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Safety Precautions This section lists important precautions which users of semiconductor devices (and anyone else) should observe in order to avoid injury and damage to property, and to ensure safe and correct use of devices. Please be sure that ...

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General Precautions regarding Semiconductor Devices Do not use devices under conditions exceeding their absolute maximum ratings (e.g. current, voltage, power dissipation or temperature). This may cause the device to break down, degrade its performance, or cause it to catch ...

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Precautions Specific to Each Product Group 2.2.1 Optical semiconductor devices When a visible semiconductor laser is operating, do not look directly into the laser beam or look through the optical system. This is highly likely to impair vision, and ...

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Do not use devices under conditions which exceed their absolute maximum ratings (current, voltage, power dissipation, temperature etc.). This may cause the device to break down, causing a large short-circuit current to flow, which may in turn cause it to ...

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General Safety Precautions and Usage Considerations This section is designed to help you gain a better understanding of semiconductor devices ensure the safety, quality and reliability of the devices which you incorporate into your designs. 3.1 ...

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Make sure that sections of the tape carrier which come into contact with installation devices or other electrical machinery are made of a low-resistance material. (f) Make sure that jigs and tools used in the assembly process do not ...

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When storing printed circuit boards which have devices mounted on them, use a board container or bag that is protected against static charge. To avoid the occurrence of static charge or discharge due to friction, keep the boards separate ...

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Storage 3.2.1 General storage • Avoid storage locations where devices will be exposed to moisture or direct sunlight. • Follow the instructions printed on the device cartons regarding transportation and storage. • The storage area temperature should be kept ...

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General Safety Precautions and Usage Considerations • If the 12-month storage period has expired the 30% humidity indicator shown in Figure 1 is pink when the packing is opened, it may be advisable, depending on the device ...

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... This section describes some general precautions which you should observe when designing circuits and when mounting devices on printed circuit boards. For more detailed information about each product family, refer to the relevant individual technical datasheets available from Toshiba. 3.3.1 Absolute maximum ratings Do not use devices under conditions in which their absolute maximum ratings (e ...

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CMOS logic IC inputs, for example, have extremely high impedance input pin is left open, it can easily pick up extraneous noise and become unstable. In this case, if the input voltage level reaches an intermediate level, it ...

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... For details of how to interface particular devices, consult the relevant technical datasheets and databooks. If you have any questions or doubts about interfacing, contact your nearest Toshiba office or distributor. 3 General Safety Precautions and Usage Considerations Ta θ ...

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Decoupling Spike currents generated during switching can cause Vcc (Vdd) and GND (Vss) voltage levels to fluctuate, causing ringing in the output waveform or a delay in response speed. (The power supply and GND wiring impedance is normally 50 ...

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Peripheral circuits In most cases semiconductor devices are used with peripheral circuits and components. The input and output signal voltages and currents in these circuits must be chosen to match the semiconductor device’s specifications. The following factors must be ...

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Inspection Sequence Do not insert devices in the wrong orientation. Make sure that the positive and negative electrodes of the power supply are correctly connected. Otherwise, the rated maximum current or maximum power dissipation may be exceeded and the ...

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If lead insertion hole intervals on the printed circuit board do not precisely match the lead pitch of the device, do not attempt to forcibly insert devices by pressing on them or by pulling on their leads. (3) For ...

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Soldering temperature profile The soldering temperature and heating time vary from device to device. Therefore, when specifying the mounting conditions, refer to the individual datasheets and databooks for the devices used. (1) Using medium infrared ray reflow • Heating ...

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... Electrical contact may also cause a chip to fail. Therefore, when mounting devices, make sure that nothing comes into electrical contact with the reverse side of the chip. If your design requires connecting the reverse side of the chip to the circuit board, please consult Toshiba or a Toshiba distributor beforehand. ...

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... When handling chips, be careful not to expose them to static electricity. In particular, measures must be taken to prevent static damage during the mounting of chips. With this in mind, Toshiba recommend mounting all peripheral parts first and then mounting chips last (after all other components have been mounted). ...

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Tightening torque (1) Make sure the screws are tightened with fastening torques not exceeding the torque values stipulated in individual datasheets and databooks for the devices used. (2) Do not allow a power screwdriver (electrical or air-driven) to touch ...

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Strong electrical and magnetic fields Devices exposed to strong magnetic fields can undergo a polarization phenomenon in their plastic material, or within the chip, which gives rise to abnormal symptoms such as impedance changes or increased leakage current. Failures ...

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General Safety Precautions and Usage Considerations 3-18 ...

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... Resonators recommended for use with Toshiba products in microcontroller oscillator applications are listed in Toshiba databooks along with information about oscillation conditions. If you use a resonator not included in this list, please consult Toshiba or the resonator manufacturer concerning the suitability of the device for your application. ...

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Precautions and Usage Considerations 4-2 ...

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TX4939 2005-11 Rev. 3.1 ...

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...

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... Space Registers.” • The notation <register name>.<bit/field name> is used to indicate a specific bit/field of a register. Example: CCFG.TOE CCFG.TOE refers to the Timeout Enable for Bus Error (TOE) field, located at bit 14 of the Chip Configuration Register (CCFG). Rev. 3.1 November 1, 2005 Toshiba RISC Processor i TX4939 ...

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... MIPS Publications PCI Local Bus Specification Revision 2.2 PCI Bus Power Management Interface Specification Revision 1.1 Audio CODEC ‘97 (AC ‘97) Revision 2.1 SmartMedia™ Physical Format Specifications Web-Online Version 1.00 SMIL (SmartMedia™ Interface Library) Software Edition Version 1.00 Rev. 3.1 November 1, 2005 Toshiba RISC Processor ii TX4939 ...

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... The TX4939 is a micro controller for the 64-bit TX System RISC TX49 family. The TX4939 uses the TX49/H4 core as its CPU. The TX49/H4 core is a 64-bit RISC CPU core that Toshiba developed based on the R4000 architecture created by MIPS Technologies, Inc. (MIPS). Refer to the TX49 Core Architecture Manual for more information on the TX49/H4 core such as the Instruction set ...

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... ATA100/ATAPI CH-0 N/A ATA100/ATAPI CH-1 Max. 2-ch 10/100 Ethernet MAC with RMII interface 1-Serial TS I/O, 1-Serial TS I/O, 1-Parallel TS/656 I/O 2-Serial TS Input SPI Interface SIO2, SIO3 ACLINK I2S 2ch / I2S 5.1ch I2C N/A 1-2 Toshiba RISC Processor TX4939 DMAC INT Battery Back Battery Back UP DMAC RTC 8-ch Chain mode SIO-0 SIO-1 ...

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... Maximum 6 Master Device Maximum 6 Master Device Figure 1-2 Two ATA100 for DVD Recorder Rev. 3.1 November 1, 2005 NOR ROM ASIC NAND ROM 16-bit Local Bus I2S/ACLINK DDR TOSHIBA DDR TX4939XBG CRYPT DDR ENGINE DDR ATA100 OSD ATA100 MPEG Bitmap Decoder MPEG CCIR656 Graphics ...

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... Maximum 6 Master Device Maximum 6 Master Device Figure 1-3 One ATA100 and Two Ethernet System Rev. 3.1 November 1, 2005 NOR ROM ASIC NAND ROM 16-bit Local Bus I2S/ACLINK DDR TOSHIBA DDR TX4939XBG CRYPT DDR ENGINE DDR ATA100 RMII x2 MPEG Decoder MPEG Graphics CODEC TS Stream Controller ...

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... BLOCK 2.1. TX4939 System Block Diagram SIO Default X32K,Bat. Regulator OSC Figure 2-1 TX4939 Internal Block Diagram Rev. 3.1 November 1, 2005 Chapter 2. Internal Block Diagram SIO2,SIO3 or SPI I2C Timer bus IM bit 32- - bus IM bit 32 IMB 2-1 Toshiba RISC Processor TX4939 I2S / ACLINK 2 2 ...

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... BLOCK 2.2. TX49/H4 Core Features The TX49/H4 core is a high-performance, low power consumption 64-bit RISC CPU core developed by Toshiba. This core has the following features. 64-bit Operation 32/64-bit Integer General-purpose Registers 64-GB Physical Address Space Optimized 5-stage Pipeline Instruction Set Upwards Compatible with MIPS III ISA Added 3-operand multiply instruction, MAC (Multiply Accumulate) instruction, PREF (pre- fetch) instruction ...

Page 67

... CPU and external terminal. The external interrupt signal can wake the CPU up by the help of external power control circuit. This RTC is designed as low power circuitry which consumes maximum. This assures 10 years battery life with conventional Lithium battery with 200 mAH capacity. The ultimate low power system can be realized with this RTC. Rev. 3.1 November 1, 2005 Toshiba RISC Processor 2-3 TX4939 2 ...

Page 68

... Low power consumption mode: Can select Self-refresh or Pre-charge Power Down. □ Advanced Memory Mapping Technology 4 (four) independent DDR memory mapping windows enable mapping the DDR memory space to anywhere TX49 physical memory space with 16 MB resolution. Rev. 3.1 November 1, 2005 Toshiba RISC Processor 2pcs (=64MB) 2pcs (=128MB) ...

Page 69

... FIFO for transmission × On-chip 13-bit 16-stage FIFO (data: 8 bits, status: 5 bits) for reception Rev. 3.1 November 1, 2005 Toshiba RISC Processor Address bus consists of 6 dedicated and 16+3 external latched A[21:6] can be latched from SADB[15:0] A[27:22] can be latched from SA[5:0] A[22:7] can be latched from SADB[15:0] A[28:23] can be latched from SA[5:0] ...

Page 70

... The basic features of the I2S controller are outlined below: □ Two modes of operation (2 channels i/o mode, 3 Channel output mode) □ Support 16, 18 bits data. □ Support Left or Right-justify with MSB first. □ Support 32 bit-wide time-slot. Rev. 3.1 November 1, 2005 Toshiba RISC Processor 2-6 TX4939 2 2 ...

Page 71

... KEY registers are W/O (write only) (c) keep initial data for each stream (d) Initial data will be updated for CBC mode (e) Decryption-KEY will be generated from Encryption-KEY without exposure □ Supports Ex-OR operation □ Modular Exponentiation Operation Coprocessor Engine Rev. 3.1 November 1, 2005 Toshiba RISC Processor 2-7 TX4939 2 2 ...

Page 72

... Can perform execution control (run, break, step, register/memory access real-time debugging function that uses dedicated emulation probes and can use PC traces. □ PC-Trace dedicated pins are multiplexed with some of Video port signal pins. □ Tamper protection for EJTAG access. Rev. 3.1 November 1, 2005 Toshiba RISC Processor 2-8 TX4939 2 2 ...

Page 73

... S149 VD0 IO AE22 S150 S152 VD3 IO AF23 S153 S155 VD6 IO AF24 S156 S158 DRDQ1 IO AD26 S159 S161 DRDM0 O AC26 S162 3-1 Toshiba RISC Processor TX4939 Class Signal_Name IO BALL BE0 CE1 INT2 INTB INTD GNT5 GNT4 ...

Page 74

... A7 S298 S300 OE S301 S303 DMAREQ0 I D6 S304 S306 SA02 IO C5 S307 S309 DMAACK1 IO B4 S310 S312 SA01 IO B3 3-2 Toshiba RISC Processor TX4939 Class Signal_Name IO BALL DRDQ6 IO AB26 DRDQ9 IO AA25 DRDM1 O Y24 DRDQ13 IO W24 DRCKE O V24 DRA8 O U23 DRA7 O U26 DRA2 ...

Page 75

... Y22, AB7, AB8, AB11, AB12, AB15, AB16, AB19, AB20 VDD33 E6, E9, E10, E13, E14, E17, E18, E21, F5, J5, K5, N5, P5, U5, V5, AA5, AB6, AB9, AB10, AB13, AB14, AB17, AB18, AB21 VDD25 F22, J22, K22, N22, P22, U22, V22, AA22 Rev. 3.1 November 1, 2005 Table 3-2 Power Pin Assignment 3-3 Toshiba RISC Processor TX4939 3 3 ...

Page 76

... Pin Assignment 3.2. Pin Alignment (TOP VIEW) Package Outl i ne TX4939XBG DMAR DMAR SADB1 SYSCL A VSS VSS SA04 OE* ACE* EQ1 EQ2 3 DMAA DMAA SADB1 SADB0 B VSS VSS SA01 SWE* VSS CK1 CK2 0 DMAA SADB1 SADB1 SADB0 C BE1* SA00 VSS SA03 SA02 ...

Page 77

... DDR Control Signals DRCAS*, DRRAS* DRCKE Output DDR Control Signals Clock Enable signal Rev. 3.1 November 1, 2005 Toshiba RISC Processor This clock is used to generate internal clock for This clock can be modulated by external SSCG generator. This clock is used to generate internal clock for 3-5 TX4939 3 3 ...

Page 78

... IO write A1_DIOR* I/O IO read A1_DMACK* I/O DMA Acknowledge A1_DRST* I/O Reset A1_DMAREQ I/O DMA Request A1_DIORDY I/O IO Channel Ready A1_DINTR I/O Interrupt Request A1_PDIAG* I/O Passed Diagnostics A1_DASP* I/O Slave Presence Note: Since All Signals can be used as GPIO, only bidirectional IO is used. Rev. 3.1 November 1, 2005 Toshiba RISC Processor 3-6 TX4939 3 3 ...

Page 79

... Rev. 3.1 November 1, 2005 Address [21:6] will appear on this bus to latch by - Together with SA[0] to determine if this is a 8-bit or 16-bit cycle ISA device use this signal to drag out the cycle, this signal is needed 3-7 Toshiba RISC Processor TX4939 These pins are also used for Boot This pin also 3 ...

Page 80

... This pin represents IDSEL input for Satellite mode. Note: With the PCI Host mode, both external and internal arbiter can be used. But the PCI Satellite mode, only external arbiter mode available. Rev. 3.1 November 1, 2005 Toshiba RISC Processor th arbiter REQ* input. th arbiter GNT* output. ...

Page 81

... This is the serial Time Division Multiplexed AC’97 output stream input. 3.3.12. I2S Interface 2-channel mode I2S Interface Signal Name I/O Function I2S_WS0 I/O Channel 0 Word Select I2S_SCK0 I/O Channel 0 Bit Clock I2S_SD0 I/O Channel 0 Data PD I2S_WS1 I/O Channel 1 Word Select I2S_SCK1 I/O Channel 1 Bit Clock I2S_SD1 I/O Channel 1 Data PD Rev. 3.1 November 1, 2005 Toshiba RISC Processor 3-9 TX4939 3 3 ...

Page 82

... This is connected with 32Khz crystal. X32OUT Output 32KHz Crystal Output This is connected with 32Khz crystal. Note: All RTC signals and RTCVDD are required independent Voltage from the system. Rev. 3.1 November 1, 2005 Toshiba RISC Processor 2 3.3 V Open drain low active signal 3-10 TX4939 3 3 ...

Page 83

... This is the PLL analog power pin. will be 1.2V power supply voltage. PLL3Vss_A – Ground for PLL3 (Audio) This is the PLL analog ground pin. Rev. 3.1 November 1, 2005 Toshiba RISC Processor PLL will be modified version of PLL3M32E, which PLL will be modified version of PLL3M32E, which 3-11 TX4939 3 3 ...

Page 84

... On, TPC[3:1] and the PCST signal are outputted synchronously. This clock is 1/3 the frequency of the TX49/H4 Core operating clock (CPUCLK). PCST [8:0] Output PC Trace Status Output These signals output information such as the PC Trace Status. Rev. 3.1 November 1, 2005 Toshiba RISC Processor When connecting an EJTAG probe, take 3-12 TX4939 3 3 ...

Page 85

... GPIO22 GPIO23 Table 3-4 I2S Signals ACLINK mode I2S 2ch ACRESET* I2S_WS0 BITCLK I2S_SCK0 SDIN[0] I2S_SD0 SDOUT I2S_WS1 SYNC I2S_SCK1 SDIN[1] I2S_SD1 3-13 Toshiba RISC Processor TX4939 Ball A15 D14 C14 B14 C18 B17 C17 A18 B18 D17 A17 C16 A16 D15 B16 ...

Page 86

... A0_DD03 G0PIO21 A0_DD11 G0PIO22 A0_DD04 G0PIO23 A0_DD10 G0PIO24 A0_DD05 G0PIO25 A0_DD09 G0PIO26 A0_DD06 G0PIO27 A0_DD08 G0PIO28 A0_DD07 G0PIO29 A0_DRST* 3-14 Toshiba RISC Processor TX4939 Ball AF3 AD4 AE4 AF4 AC5 AD5 AE5 AF5 AC6 AD6 AE6 AF6 AC7 AD7 AF7 AC8 AD8 ...

Page 87

... E1MDC A1_DD11 E1MDIO A1_DD04 G1PIO22 A1_DD10 G1PIO23 A1_DD05 G1PIO24 A1_DD09 G1PIO25 A1_DD06 G1PIO26 A1_DD08 G1PIO27 A1_DD07 G1PIO28 A1_DRST* G1PIO29 3-15 Toshiba RISC Processor TX4939 Ball AF11 AC12 AD12 AF12 AC13 AD13 AE13 AF13 AF14 AE14 AD14 AC14 AF15 AD15 AC15 AF16 AE16 ...

Page 88

... PCT[2] VDPSN PCT[3] VD0 PCT[4] VD1 PCT[5] VD2 PCT[6] VD3 PCT[7] VD4 PCT[8] VD5 G2PIO15 VD6 G2PIO16 VD7 3-16 Toshiba RISC Processor TX4939 3-Serial Mode Ball VDCLKIN1 AC19 VDCLKO1 AF20 VDVLD1 AD20 VDPSN1 AC20 VDS1 AF21 VDCLKIN2 AE21 VDCLKO2 AD21 VDVLD2 AC21 ...

Page 89

... PCICLK is OFF and IOSRST* will be assert during RESET* assertion. During PCICLK[4] is ON, IOSRST function will be disengaged PCICLK PCICLK is OFF and SYSRST* will be deassert by RESET* assertion. During PCICLK[3] is ON, SYSRST function will be disengaged PCICLK PCICLK is OFF at boot time PCICLK PCICLK boot time 3-17 Toshiba RISC Processor TX4939 3 3 ...

Page 90

... Pin Assignment Rev. 3.1 November 1, 2005 Toshiba RISC Processor 3-18 TX4939 3 3 ...

Page 91

... All PLL Powers MSTCLK, MSTCLK2 Stabilized Time MSTCLK, MSTCLK2 Boot Configuration Inputs Stabilized Time SA[5:0] DMAACK[2:0] SADB[15:0] All PLL Stabilized Time + Synchronous Reset Propagation Time RESET* Figure 4-1 Boot Configuration Settling Timing Rev. 3.1 November 1, 2005 Chapter 4. Boot Configuration T RESETW 4-1 Toshiba RISC Processor TX4939 4 4 ...

Page 92

... DIV6 of Gbus clock 1 : Enable 0 : Disabled YDIVMODE[2:0] CPUCLK/GBUSCLK 000 (1 / 2.0) 001 (1 / 3.0) 110 (1 / 5.0) 111 ( Trace Enable Trace Disable Boot ROM Bus Width 16 bit 8 bit 4-2 Toshiba RISC Processor TX4939 Corresponding Register Bit MULCLK[2: SYSSP[1:0] SSCG CCFG_PCIMODE YDIVMODE[2:0] CCFG_PTSEL CCFG_BESEL CCFG_ACKSEL CCFG_ROMW CCFG_ENDIAN CCFG_TINTDIS ...

Page 93

... Indicates the PCI bus arbiter selection setting 0 = Select external PCI bus arbiter 1 = Select built-in PCI bus arbiter SADB[7] PCI Boot Option 0 = PCI Boot off 1 = PCI Boot on SADB[15:8] Reserved for software setting. Rev. 3.1 November 1, 2005 Toshiba RISC Processor 4-3 TX4939 Corresponding Register Bit CCFG_ARB CCFG_PCIBOOT CCFG_BCFG[7:0] ...

Page 94

... Boot Configuration Rev. 3.1 November 1, 2005 Toshiba RISC Processor 4-4 TX4939 ...

Page 95

... MHz 400.00 MHz 433.33 MHz 466.66 MHz Div 2 Div 2 33/66 MHz PCI Service Clocks Figure 5-1 Overview of Clocking System in TX4939 Rev. 3.1 November 1, 2005 Toshiba RISC Processor Chapter 5. Clock Generators FS*512 CH0 Audio Clock Audio Clock FS*512 CH1 Generator Generator Baud rate PLL ...

Page 96

... CPUCLK CN CK GBUSCLK FS[0] DDRCLK ND[4:0] IMBUSCLK CG for RCLK2 CPUCLK RCLK3 RCLK4 SYSCLK RESET_INT Figure 5-2 Master Clock Generator 5-2 Toshiba RISC Processor TX4939 UART I2S I2S CIR BAUD2 UART 100 MHz ATA100 66 MHz PCI66S CPUCLK 333 / 400 MHz 166 / 200 MHz GBUSCLK DDRCLK 166 / 200 MHz ...

Page 97

... FN PLL3M32K C2S RS[3:0] from IS[1:0] CK Register FS[1:0] ND[4:0] BAUD for UART CLK4MHZ Rev 1.04 5/17/2005 Figure 5-3 Diagram of Audio Clock Generator Rev. 3.1 November 1, 2005 Toshiba RISC Processor 45.1584 MHz (88.2 KHz) DIV10 22.5792 MHz (44.1 KHz) DIV2 49.1520 MHz (96.0 KHz) DIV2 24.576 MHz (48.0 KHz) DIV4 16.384 MHz (32.0 KHz) DIV6 12 ...

Page 98

... OS 1 33,868,800 Hz 1 16,934,400 Hz 32 36,864,000 Hz 32 18,432,000 Hz 32 12,288,000 Hz 32 9,216,000 Hz 32 6,144,000 Hz 32 3,072,000 Hz 8 11,059,200 Hz 5-4 Toshiba RISC Processor TX4939 ). The SOURCE Fs*512 Fs*256 88,200 Hz 176,400 Hz 44,100 Hz 88,200 Hz 96,000 Hz 192,000 Hz 48,000 Hz 96,000 Hz 32,000 Hz 64,000 Hz 24,000 Hz 48,000 Hz 16,000 Hz 32,000 Hz 8,000 Hz ...

Page 99

... KHz x 512) 10 45,157,895 Hz Actual (=88.199 KHz x 512) 49,152,000 Hz Target 16 (=96.0 KHz x 512) 147 49,151,450 Hz Actual (=95.999 KHz x 512) 14,745,600 Hz Target 8 (=921.6 KHz x 16) 245 14,745,435 Hz Actual (=921.590 KHz x 16) 5-5 Toshiba RISC Processor TX4939 Divisor 192 96 192 96 Divisor N/A N/A N/A ...

Page 100

... PLL mode, such as Integer PLL. Since 19/429 is about 1/22, the integer multiplier is better to close to 22. In this design, X20 is chosen for that mode. In this mode, 20 MHz external clock should be changed to 22.5792 MHz instead. This clock can be available from any of Audio Clock Generator. Rev. 3.1 November 1, 2005 Toshiba RISC Processor Result Logic Clock Actual Sampling Clock 49 ...

Page 101

... This multiplication factor is power of 2, these jitter will be disappeared after dividing 5-7 Toshiba RISC Processor TX4939 ...

Page 102

... Toshiba RISC Processor TX4939 This Div 2 Div 2 Div 2 3.072MHz 1.536MHz 32fs 16fs 8fs 64fs 32fs 16fs 128fs 64fs 32fs - - - - - - ...

Page 103

... C2S R/W R/W R/W R MFRAC MINTL FS[1:0] 1’b1 1’b1 2’b00 1’b0 1’b1 2’b00 1’b1 1’b1 2’b01 1’b0 1’b1 2’b01 1’b1 1’b0 2’b00 1’b1 1’b0 2’b01 5-9 Toshiba RISC Processor TX4939 R/O R/O R MFRAC MINTL R/O R/W R [3:0] R/W R/W R ...

Page 104

... M Hz 175 M Hz 250 M Hz 350 M Hz 500 113 M Hz 158 M Hz 225 M Hz 5-10 Toshiba RISC Processor TX4939 High Limit 450 MHz 1,000 MHz 315 MHz 700 MHz 225 MHz 500 MHz 158 MHz 350 MHz ...

Page 105

... RESERVED R/O R/O R/O R RESERVED R/O R/O R/O R RESERVED R/O R/O R/O R CHB CAE R/W R/W R/W R Table 5-12 Bit Field Definitions 5-11 Toshiba RISC Processor TX4939 R/O R/O R R/O R/O R R/O R/O R CHA R/W R/W R ...

Page 106

... MHz. In addition, it will be SSCG modulated when SSCGEN signal asserted. Because of this nature not recommended to use this Baud-rate for communication through MODEM or external line. But it is suitable to use in the system to control peripherals like LCD panel or remote control equipment. Rev. 3.1 November 1, 2005 Toshiba RISC Processor 5-12 TX4939 5 ...

Page 107

... The SSCG UNIT in TX4939 modulates MSTCLK directly. This SSCG module does frequency modulation by pure digital circuit. MSTCLK 20MHz CKIN SSCG SSCGEN 5.5.2. Modulation Profile Modulation Magnitude = 0.5% (p-p) Modulation Frequency = 31.25 KHz Maximum Delay Time = 516 steps (19.09 nS) Rev. 3.1 November 1, 2005 400 MHz X 20 CKOUT PLL#1 PLL#1 FS[0] BP ND[4:0] Figure 5-8 Location of SSCG UNIT 5-13 Toshiba RISC Processor TX4939 ...

Page 108

... Figure 5-10 Structure of DDR Clock De-Skew Circuit Rev. 3.1 November 1, 2005 CIN OUT = “dll_dskw1” Reference SCK REF EN Same RST Delay CIN OUT “dll_dskw1” ALL DDR ALL DDR SCK REF LOGIC LOGIC 5-14 Toshiba RISC Processor TX4939 Mother Board Motherboard DRCKP DRCKM DRCKOUT DRCKREF ...

Page 109

... PCI De-Skew is performed by PLL circuit. Figure 5-11 shows this diagram and recommended PCI Clock distribution. PCI66S div 2 div 2 33/66 MHz PCICLK1 PCI Service Clocks Figure 5-11 Structure of PCI Clock De-Skew Circuit Rev. 3.1 November 1, 2005 Toshiba RISC Processor PCI CG PCI Clock Tree Logic PLL PCICLKIN Same timing point in terms of PCI Clock Positive Edge ...

Page 110

... CG Rev. 3.1 November 1, 2005 Toshiba RISC Processor 5-16 TX4939 5 5 ...

Page 111

... GB 0xF_C000_0000 0xF_BFFF_FFFF ksseg 0.5 GB 0xF_A000_0000 0xF_9FFF_FFFF 0.5 GB kseg1 0xF_8000_0000 0xF_7FFF_FFFF 0.5 GB 0xF_6000_0000 0xF_5FFF_FFFF kseg0 0.5 GB 0x0_C000_0000 0x0_BFFF_FFFF 0.5 GB 0x0_A000_0000 0x0_9FFF_FFFF 0.5 GB 0x0_8000_0000 0x0_7FFF_FFFF kuseg 0.5 GB 0x0_6000_0000 0x0_5FFF_FFFF 0.5 GB 0x0_4000_0000 0x0_3FFF_FFFF 0.5 GB 0x0_2000_0000 0x0_1FFF_FFFF 0.5 GB 0x0_0000_0000 6-1 Toshiba RISC Processor TX4939 INTERNAL REGISTER PHYSICAL: 0xF_FF00_0000 BOOT ADDRESS PHYSICAL: 0x0_1FC0_0000 Rev 2. ...

Page 112

... Registers 1.0 GB 0xF_C000_0000 0xF_BFFF_FFFF 1.0 GB 0xF_8000_0000 0xF_7FFF_FFFF 1.0 GB 0x0_4000_0000 0x0_3FFF_FFFF 0.5 GB 0x0_2000_0000 0x0_1FFF_FFFF 0.5 GB 0x0_0000_0000 Figure 6-2 Physical Address Map at Initializing System Rev. 3.1 November 1, 2005 Toshiba RISC Processor ENLARGED BOOT BLOCK ENLARGED BOOT BLOCK 0x0_1FFF_FFFF 0x0_1FFF_FFFF 32 MB 0x0_1FC0_0000 0x0_1FBF_FFFF 0x0_1F80_0000 128 MB 0x0_1F7F_FFFF 0x0_1F40_0000 0x0_1F3F_FFFF 0x0_1800_0000 0x0_1F00_0000 0x0_1EFF_FFFF ...

Page 113

... Rev. 3.1 November 1, 2005 Toshiba RISC Processor Register Symbol Register Name DRWINEN Enable/Disable DDR Mapping Windows DRWIN00 DDR Mapping Window #0 DRWIN01 DDR Mapping Window #1 DRWIN02 DDR Mapping Window #2 DRWIN03 DDR Mapping Window #3 6-3 ...

Page 114

... Drive Strength Control of DRCAS Control is same as above Drive Strength Control of DRRAS Control is same as above Drive Strength Control of DRCKE Control is same as above 1'b1 = Enable Window #3, 1'b0 = Disable 1'b1 = Enable Window #2, 1'b0 = Disable 1'b1 = Enable Window #1, 1'b0 = Disable 1'b1 = Enable Window #0, 1'b0 = Disable 6-4 Toshiba RISC Processor TX4939 0x8200 DCBA R/W R/W : R/W 2’b00 ...

Page 115

... Define the offset address of the target DDR memory space. DRWINOF _ADRS = { DRWINOF [29:20], 20'H0_0000 } ⎯ Define corresponding DDR channel number with CS CS[1: Channel 0 (CS0) CS[1: Channel 0 (CS0) CS[1: Channel 1 (CS1) CS[1: Channel 1 (CS1) NOTE: CS setting should be consistent with DDR_CTRL15 setting. 6-5 Toshiba RISC Processor TX4939 0x8210 0x8218 0x8220 ...

Page 116

... BOOT CODE 128 MB 0x0_1800_0000 0x0_17FF_FFFF 128 MB 0x0_1000_0000 0x0_0FFF_FFFF 128 MB 0x0_0800_0000 0x0_07FF_FFFF 128 MB 0x0_0000_0000 Figure 6-5 Example of DDR Memory Split-Mapping Rev. 3.1 November 1, 2005 Toshiba RISC Processor 0x3FFF_FFFF DRWIN#0 (ENABLE) DRWINUP 0x17FF_FFFF DRWINLO 0x0000_0000 DRWINOF 0x0000_0000 DRWINCS 0x0 (CS0) DRWIN#1 (ENABLE) DRWINUP 0xA7FF_FFFF DRWINLO ...

Page 117

... Indicates that memory is prefetchable. 0: Indicates that memory is not prefetchable. Type (Default: 00) 00: Indicates that an address is within a 32-bit address region Memory Space Indicator (Fixed Value Indicates that this Base Address Register is for use by the PCI Memory Space 6-7 Toshiba RISC Processor TX4939 RESERVED R/O R/O ...

Page 118

... Toshiba RISC Processor TX4939 Memory Size 512 256 128 ...

Page 119

... Big/Little Endian Address (Bit which are accessed) [63….....32] [31….....0] ######## [63….....32] [31….....0] ######## 6-9 Toshiba RISC Processor TX4939 Physical Address 1 Physical Address 2 Little Endian ######## 6 6 ...

Page 120

... Crypt Engine PCIC1 (For Ethernet MAC[1:0] ) DDR (including DDR mapping register EBUSC VPC DMAC0 DMAC1 Reserved PCIC CONFIG/GPIO IRC TMR0 TMR1 TMR2 SIO0, SIO2 SIO1, SIO3 Reserved Reserved ACLC SPIC I2C I2S RTC CIR TMR3 TMR4 TMR5 6-10 Toshiba RISC Processor TX4939 6 6 ...

Page 121

... ATAPI Packet Command for ATA0 ATA0_Bxfer_cntH Bus Transfer Count High for ATA0 ATA0_Bxfer_cntL Bus Transfer Count Low for ATA0 ATA0_Dev_TErr Device Timing Error for ATA0 ATA0_Pkt_xfer_ct Packet Transfer Control for ATA0 ATA0_Strt_AddT Transfer Start Top Address for ATA0 6-11 Toshiba RISC Processor TX4939 Register Name 6 6 ...

Page 122

... NAND Flash Memory Mode Control Register NDFSR NAND Flash Memory Status Register NDFISR NAND Flash Memory Interrupt Status Register NDFIMR NAND Flash Memory Interrupt Mask Register NDFSPR NAND Flash Memory Strobe Pulse Width Register 6-12 Toshiba RISC Processor TX4939 Register Name Register Name 6 6 ...

Page 123

... Context Data Register 3 Cdr4 Context Data Register 4 Cdr5 Context Data Register 5 Cdr6 Context Data Register 6 Cdr7 Context Data Register 7 Cdr8 Context Data Register 8 Cdr9 Context Data Register 9 -- Reserved -- Reserved -- Reserved -- Reserved -- Reserved -- Reserved 6-13 Toshiba RISC Processor TX4939 Register Name Register Name 6 6 ...

Page 124

... PCI Bus Arbiter Status Register PBAMASK PCI Bus Arbiter Interrupt Mask Register PBABM PCI Bus Arbiter Broken Master Register PBACREQ PCI Bus Arbiter Current Request Register PBACGNT PCI Bus Arbiter Current Grant Register PBACSTATE PCI Bus Arbiter Current State Register 6-14 Toshiba RISC Processor TX4939 6 6 ...

Page 125

... P2G Memory Space 2 G-bus Base Address Register P2GIOGBASE P2G I/O Space G-bus Base Address Register G2PCFGADRS G2P Configuration Address Register G2PCFGDATA G2P Interrupt Acknowledge Data Register G2PINTACK G2P Interrupt Acknowledge Data Register G2PSPC G2P Special Cycle Data Register 6-15 Toshiba RISC Processor TX4939 6 6 ...

Page 126

... Rev. 3.1 November 1, 2005 Toshiba RISC Processor Register Symbol Register Name DDRCTL00 DDR_CTL_00 DDRCTL01 DDR_CTL_01 DDRCTL02 DDR_CTL_02 DDRCTL03 DDR_CTL_03 DDRCTL04 DDR_CTL_04 DDRCTL05 DDR_CTL_05 DDRCTL06 DDR_CTL_06 DDRCTL07 DDR_CTL_07 DDRCTL08 ...

Page 127

... Rev. 3.1 November 1, 2005 Toshiba RISC Processor Register Symbol Register Name EBCCR0 EBUS Channel Control Register 0 EBCCR1 EBUS Channel Control Register 1 EBCCR2 EBUS Channel Control Register 2 EBCCR3 EBUS Channel Control Register 3 EBCCR4 EBUS Channel Control Register 4 (Reserved) ...

Page 128

... Rev. 3.1 November 1, 2005 Toshiba RISC Processor Register Register Name Symbol DM0CHAR0 DMAC0 Chain Address Register 0 DM0SAR0 DMAC0 Source Address Register 0 DM0DAR0 DMAC0 Destination Address Register 0 DM0CNTR0 DMAC0 Count Register 0 DM0SAIR0 DMAC0 Source Address Increment Register 0 ...

Page 129

... Rev. 3.1 November 1, 2005 Toshiba RISC Processor DM0CCR3 DMAC0 Channel Control Register 3 DM0CSR3 DMAC0 Channel Status Register 3 DM0MFDR DMAC0 Memory Fill Data Register DM0MCR DMAC0 Master Control Register Register Register Name Symbol DM1CHAR0 ...

Page 130

... PCI Bus Arbiter Interrupt Mask Register PBABM PCI Bus Arbiter Broken Master Register PBACREQ PCI Bus Arbiter Current Request Register (for a diagnosis) PBACGNT PCI Bus Arbiter Current Grant Register (for a diagnosis) PBACSTATE PCI Bus Arbiter Current Status Register (for a diagnosis) 6-20 Toshiba RISC Processor TX4939 Register Name 6 6 ...

Page 131

... Rev. 3.1 November 1, 2005 Toshiba RISC Processor Register Register Name Symbol G2PM0GBASE G2P Memory Space 0 G-Bus Base Address Register G2PM1GBASE G2P Memory Space 1 G-Bus Base Address Register G2PM2GBASE G2P Memory Space 2 G-Bus Base Address Register ...

Page 132

... Rev. 3.1 November 1, 2005 Toshiba RISC Processor PDMCTR PDMAC Count Register PDMCFG PDMAC Configuration Register PDMSTATUS PDMAC Status Register Register Register Name Symbol CCFG Chip Configuration Register REVID Chip Revision ID Register PCFG ...

Page 133

... TMCCDR5 0xFF40 32 TMWTMR5 0xFFF0 32 TMTRR5 Rev. 3.1 November 1, 2005 Toshiba RISC Processor Register Name Timer Control Register 0 Timer Interrupt Status Register 0 Compare Address Register A 0 Compare Address Register B 0 Interval Timer Mode Register 0 Divider Register 0 Pulse Generator Mode Register 0 Timer Read Register 0 ...

Page 134

... SIBGR3 0xF49C 32 SITFIFO3 0xF4A0 32 SIRFIFO3 Rev. 3.1 November 1, 2005 Toshiba RISC Processor Register Name Line Control Register 0 DMA/Interrupt Control Register 0 DMA/ Interrupt Status Register 0 Status Change Interrupt Status Register 0 FIFO Control Register 0 Flow Control Register 0 Baud Rate Control Register 0 Transmitter FIFO Register 0 ...

Page 135

... IRRCNT 0xE920 32 IRMASKINT 0xE928 32 IRMASKEXT Rev. 3.1 November 1, 2005 Toshiba RISC Processor Register Name Interrupt Detection Enable Register Interrupt Source and Cause Binding Register Interrupt Detection Mode Register 0 Interrupt Detection Mode Register 1 Interrupt Level Register 0 Interrupt Level Register 1 Interrupt Level Register 2 Interrupt Level Register 3 ...

Page 136

... SPSR 0xF818 32 SPDR 0xF81C 32 - Rev. 3.1 November 1, 2005 Toshiba RISC Processor Register Name ACLC Control Enable Register ACLC Control Disable Register ACLC CODEC Register Access Register ACLC Interrupt Status Register ACLC Interrupt Masked Status Register ACLC Interrupt Enable Register ACLC Interrupt Disable Register ...

Page 137

... Address (bit) CIR Controller LW/SW LE/BE 0xFC00 32 IRC_CSR Rev. 3.1 November 1, 2005 Toshiba RISC Processor Register Name I2C Interrupt Control/Status Register I2C Transmit/Receive Register I2C Command Register I2C Prescale Register I2C Control Register Register Name I2S Channel Main Control Register I2S Channel Control Register ...

Page 138

... Address Rev. 3.1 November 1, 2005 Toshiba RISC Processor 6-28 TX4939 6 6 ...

Page 139

... Refer to the descriptions of each controller for details. If the TRST* signal is deasserted assumed that an EJTAG probe is connected, so the G-Bus timeout detection feature is disabled. Rev. 3.1 November 1, 2005 Chapter 7. Configuration Registers 7-1 Toshiba RISC Processor TX4939 7 7 ...

Page 140

... Any address not defined in this table is reserved for future use. Rev. 3.1 November 1, 2005 Toshiba RISC Processor Register Symbol Register Name CCFG Chip Configuration Register REVID Chip Revision ID Register PCFG Pin Configuration Register TOEA Timeout Error Access Address Register ...

Page 141

... GTOT R/W 2'b11 SSCG MULCLK R/O R/O SA[5] SA[2: YDIVMODE PTSEL RO R/W { DMAACK[1], DMAACK[1:0] } SADB[ ROMW Reserved ENDIAN ARMODE R/O R/O R/O R/W SADB[3] 0 SADB[4] 7-3 Toshiba RISC Processor TX4939 0xE000 R/W : Default R/W : Default 41 40 WDREXEN R/W : R/W : Default R/W : Default 25 24 TINTDIS R/O : R/W ~SADB[5] : Default 17 16 BEOW RW1C : R Default 9 8 BESEL ...

Page 142

... Used to inform the device connected to the PCI bus that a 66 MHz operation performed Perform a 33 MHz operation Perform a 66 MHz operation. Indicates the PCI Host/Satellite selection setting 1 = Host 0 = Satellite ⎯ bypassed 0 = SSCG Disabled (Bypass SSCG Enabled 7-4 Toshiba RISC Processor TX4939 Initial Value R/W ⎯ ⎯ SADB[7] R/O 0 RW1C 0 R/W ...

Page 143

... SYSCLK frequency = GBUSCLK frequency ÷ 6 channel0 0 = External ACK mode 1 = Normal mode Specifies the data bus width when booting from a memory device connected to the local bus controller ROMW = 1' bits ROMW = 1' bits 7-5 Toshiba RISC Processor TX4939 Initial Value R/W SA[2:0] R/O CPU Clock 300 MHz 333 MHz ...

Page 144

... Specifies the hold time of an address relative to the external bus controller ACE* signal (refer to Section 7.3.4 Switch the address at the same time when the ACE* signal is deasserted Switch the address one clock cycle after the ACE* signal is deasserted. 7-6 Toshiba RISC Processor TX4939 Initial Value R/W --- R/O SADB[4] ...

Page 145

... Indicates the minor extra code. Code 7:4 MJREV Major Revision Indicates the major revision of the product. Code Contact Toshiba technical staff for the latest information. 3:0 MINREV Minor Revision Indicates the minor revision of the product. Code Contact Toshiba technical staff for the latest information. ...

Page 146

... RESERVED SYSCLKEN RESERVED R PCICLKEN[4:1] R/W R SPEED0 RESERVED R DMASEL2 DMASEL1 R/W 0 Figure 7-3 Pin Configuration Register 7-8 Toshiba RISC Processor TX4939 0xE010 57 56 RESERVED R Default 49 48 RESERVED : R/W : Default 41 40 ATA0MODE R/W R Default 33 32 BP_PLL R/O : R/W BYPASPLL : Default R/W : Default ...

Page 147

... Specifies whether to output the SYSCLK Clock output 0 = Tri-state ⎯ PCICLK4 Enable 0: IOSRST* 1: Clock output PCICLK3 Enable 0: SYSRST* 1: Clock output PCICLK2 Enable Clock output PCICLK1 Enable Clock output 7-9 Toshiba RISC Processor TX4939 Initial Value R/W 11 R/W 1 R/W 0 R/W 11 R/W 1 R/W ⎯ ⎯ 1 R/W ⎯ ...

Page 148

... Selects a DMA request used by DMA controller 0 channel 2. 0: DMAREQ[2] (external) 1: SIO channel 0 reception (internal) Selects a DMA request used by DMA controller 0 channel 1. 00: DMAREQ[1] (external) 01: Reserved 7-10 Toshiba RISC Processor TX4939 ⎯ ⎯ 0 R/W 0 R/W ⎯ ⎯ ...

Page 149

... TOEA[31:16] R/O 0x0000 TOEA[15:0] R/O 0x0 Description ⎯ Holds the G-Bus address for the G-Bus cycle in which the latest G-Bus timeout error was detected. 7-11 Toshiba RISC Processor TX4939 0xE018 R/W : Default TOEA[35:32] R Default R/W : Default ...

Page 150

... RESERVED ETH1RST ATA1RST BROMRST R/W R SRAMRST PCI1RST DMA1RST ACLRST R/W R/W R TM0RST TM1RST TM2RST SIO0RST R/W R/W R Figure 7-5 Clock Control Register 7-12 Toshiba RISC Processor TX4939 0xE020 57 56 SIO2CKD R/W R Default 49 48 NDCCKD R/W R Default 41 40 ATA0CKD R/W R Default 33 32 CYPCKD R/W R/W : R/W ...

Page 151

... Do not supply clock pulses. 39 DMA0CKD DMAC0 Clock Controls clock pulses for the DMA controller 0. Disable 0 = Supply clock pulses not supply clock pulses. Rev. 3.1 November 1, 2005 Table 7-6 Clock Control Register Description 7-13 Toshiba RISC Processor TX4939 Initial Read/Write Value ⎯ ⎯ 0 R/W 0 R/W 0 ...

Page 152

... Normal state 1 = Reset 17 BROMRST BROM Reset Resets the BROM controller Normal state 1 = Reset 16 NDCRST NDC Reset Resets the NAND Flash controller Normal state 1 = Reset Rev. 3.1 November 1, 2005 Table 7-6 Clock Control Register Description 7-14 Toshiba RISC Processor TX4939 Initial Read/Write Value 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 ...

Page 153

... Normal state 1 = Reset 1 SIO0RST SIO0 Reset Resets the SIO0 controller Normal state 1 = Reset 0 CYPRST CYP Reset Resets the CYP controller Normal state 1 = Reset Rev. 3.1 November 1, 2005 Table 7-6 Clock Control Register Description 7-15 Toshiba RISC Processor TX4939 Initial Read/Write Value 0 R/W 0 R/W 0 R/W 0 R/W 1 R/W 0 R/W 0 ...

Page 154

... PCI controller 0001 = PDMAC 0010 = DMAC0 0011 = DMAC1 0100 = PCI controller 1 0101 = ATA0 0110 = ATA1 0111 = CYP 1000 = VPC controller A priority of PCIC > PDMAC > DMAC0 > DMAC1 > PCIC1 > ATA0 > ATA1 > CYP > VPC is initially set up. 7-16 Toshiba RISC Processor TX4939 0xE030 R/W : Default ...

Page 155

... It holds the high-order 20 bits of a register address. The default built-in register base address is 0xF_FF1F_0000. Even after the content of the base address register is changed, the default value can be used to reference the built-in registers. (Refer to "4.2 Register Mapping".) 7-17 Toshiba RISC Processor TX4939 0xE048 R/W : Default ...

Page 156

... RESERVED RESERVED R/W Description ⎯ Controls enabling of DDR DLL Locking. 2’b00 = Disable DLL Locking and force zero delay. 2’b01 = Reserved 2’b10 = Reserved 2’b11 = Always Enable Locking. ⎯ 7-18 Toshiba RISC Processor TX4939 0xE060 R/W : Default R/W : Default R/W : Default ...

Page 157

... IS[1:0] Description Charge Pump Current will 24uA) 2’b00 Charge Pump Current will 16uA) 2’b01 2’b10 Charge Pump Current will 8uA) 2’b11 Disable Charge Pump 7-19 Toshiba RISC Processor TX4939 0xE068 R/O R/O R MFRAC ...

Page 158

... RESERVED R/O R/O R/O R RESERVED R/O R/O R/O R RESERVED R/O R/O R/O R CHB R/W R/W R/W R Table 7-11 Bit Field Definitions Description 7-20 Toshiba RISC Processor TX4939 0xE070 R/O R/O R R/O R/O R R/O R/O R CHA R/W R/W R ...

Page 159

... Description RESERVED G0PIO29-G0PIO00 Mode select 0: Tri-state mode (G0PD=1), Low output (G0PD=0) 1: output mode Please refer to GPIODR1 register RESERVED GPIO23-GPIO00 Mode select 0: Tri-state mode (GPD=1), Low output (GPD=0) 1: output mode Please refer to GPIODR1 register 7-21 Toshiba RISC Processor TX4939 0xE100 R/W : Default R/W ...

Page 160

... If GPM = 0 then if GPD = 0, GPIOC drives LOW if GPD = 1, GPIOC tri-state (default GPM = 1 then if GPD = 0, GPIOC drives LOW if GPD = 1, GPIOC drives HIGH (default) When read these bits, the read data are from the GPIO signals. 7-22 Toshiba RISC Processor TX4939 0xE108 R/W : Default 34 ...

Page 161

... Reserved G2PIO16-G2PIO00 Mode select 0: Tri-state mode (G2PD=1), Low output (G2PD=0) 1: output mode Please refer to GPIODR2 register Reserved G1PIO29-G1PIO00 Mode select 0: Tri-state mode (G1PD=1), Low output (G1PD=0) 1: output mode Please refer to GPIODR2 register 7-23 Toshiba RISC Processor TX4939 0xE110 G2PM[16 : R/W : Default 34 33 ...

Page 162

... If G1PM = 0 then if G1PD = 0, GPIOC drives LOW if G1PD = 1, GPIOC tri-state (default G1PM = 1 then if G1PD = 0, GPIOC drives LOW if G1PD = 1, GPIOC drives HIGH (default) When read these bits, the read data are from the GPIO signals. 7-24 Toshiba RISC Processor TX4939 0xE118 G2PD[16] : R/W : Default ...

Page 163

... Can select either edge detection or level detection for each external interrupt when in the interrupt detection mode. The Interrupt Controller contains a 16-bit readable/write-able flag register which can be programmed to issue interrupt requests to external devices as well as to the TX49/H4 core (IRC interrupt). Rev. 3.1 November 1, 2005 Toshiba RISC Processor Chapter 8. Interrupt Controller 8-1 TX4939 8 ...

Page 164

... Process Priority 1 NANDC 1 VIDEO IRC (Internal Interrupt Request) Flag Register Polarity Register Mask Register Interrupt Control Register 8-2 Toshiba RISC Processor TX4939 Internal Interrupt Signal Non-maskable Interrupt Signal (NMI*) (active Low) Watch-dog timer Interrupt (TMR2) (active Low) External Interrupt Request REQ[1]*/INTOUT Rev 1 ...

Page 165

... Interrupt Detection Interrupt Level Interrupt Mask Mode IRDM0-1 IRLVL0-7 Level IRMSK Low Level High Level 1 3 Encoder Negative Edge Interrupt Positive Pending Edge IRPND Interrupt Prioritization 3 3 8-3 Toshiba RISC Processor TX4939 1 IP [7] Interrupt IRCS.FL Interrupt Cause 5 IRCS.CAUSE IP [6:2] 3 Interrupt Level IRCS.LVL 8 8 ...

Page 166

... In addition to above interrupt sources, the TX49/H4 core has a TX49/H4 core internal timer interrupt and two software interrupts, but these interrupts are directly reported to the TX49/H4 core independent of this Interrupt Controller. Please refer to the 64-bit TX System RISC TX49/H4 Core Architecture Manual for more information. Rev. 3.1 November 1, 2005 Toshiba RISC Processor 8-4 TX4939 8 ...

Page 167

... Low Active 45 31 Low Active 46 31 Low Active 47 31 Low Active 48 31 Low Active 49 31 Low Active 50 31 (See 8.4.2) 8-5 Toshiba RISC Processor TX4939 Compatible Mode IP[7:2] (Note 1) IP[2] 0 6’b000000 1 6’b0SSSS1 1 6’b0SSSS1 1 6’b0SSSS1 1 6’b0SSSS1 1 6’b0SSSS1 1 6’b0SSSS1 1 6’b0SSSS1 1 6’ ...

Page 168

... When the interrupt level (IRLVLn.ILm) of the currently selected interrupt changes to a value smaller than the current setting. When the currently selected interrupt is cleared (refer to 8.3.10 Clearing Interrupt Requests). Rev. 3.1 November 1, 2005 Table 8-2 Interrupt Levels Priority Interrupt Level (IRLVLn.ILm) High 111 110 101 100 011 010 Low 001 Mask 000 8-6 Toshiba RISC Processor TX4939 8 8 ...

Page 169

... Rev. 3.1 November 1, 2005 IP[6:3] If IRCS.CAUSE < 31, CP0 IP[6:3] <= 0x0F && (IRCS.CAUSE) If IRCS.CAUSE > 31, CP0 IP[6:3] <= 15 LOGICALLY, THIS DOES NOT HAVE MUCH MEANING. IP[6:3] Indicate occurrence of selected interrupt Indicate occurrence of selected interrupt 8-7 Toshiba RISC Processor TX4939 IP[2] Indicate occurrence of any interrupt Indicate occurrence of any interrupt ...

Page 170

... PCI device for example). The bit value at this time will not change even if “0” is written. This register sends interrupt notification from the TX49/H4 core to external devices. External devices can be used in applications that clear these interrupt notifications. Rev. 3.1 November 1, 2005 Toshiba RISC Processor Internal Interrupt Request (0: Request present) ...

Page 171

... Interrupt Debug Register 0 Interrupt Debug Register 1 Interrupt Debug Enable Register Interrupt Request Flag Register 0 Interrupt Request Flag Register 1 Interrupt Request Polarity Control Register Interrupt Request Control Register Interrupt Request Internal Interrupt Mask Register Interrupt Request External Interrupt Mask Register 8-9 Toshiba RISC Processor TX4939 8 8 ...

Page 172

... Interrupt Detection Enable Rev. 3.1 November 1, 2005 Reserved Explanation Reserved Interrupt Detection Enable (Default: 0) Enables interrupt detection. 0: Stop interrupts detection. 1: Start interrupts detection. 8-10 Toshiba RISC Processor TX4939 0xE800 Type : Default IDE R/W : Type 0 : Default Read/Write ⎯ R ...

Page 173

... CP0 IP[6] bit same time. Note: Interrupt source number is defined in Table 8 Assignment (Default Interrupt Source N (N>0) assigned this IP bit IP[5] interrupt source bind (Ditto) IP[4] interrupt source bind (Ditto) IP[3] interrupt source bind (Ditto) 8-11 Toshiba RISC Processor TX4939 Type : Default Type ...

Page 174

... Falling edge active 11: Rising edge active Interrupt Source Control 4 (Default: 00) Ditto Interrupt Source Control 3 (Default: 00) Ditto Interrupt Source Control 2 (Default: 00) 00: Low level active 01: Reserved 10: Reserved 11: Reserved Interrupt Source Control 1 (Default: 00) Ditto 8-12 Toshiba RISC Processor TX4939 0xE810 IC17 R/W : Type Default 2 1 ...

Page 175

... Ditto Interrupt Source Control 14 (Default: 00, R/W)) Ditto Interrupt Source Control 13 (Default: 00, R/W)) Ditto Interrupt Source Control 12 (Default: 00, R/W)) Ditto Interrupt Source Control 11 (Default: 00, R/W)) Ditto Interrupt Source Control 10 (Default: 00, R/W)) Ditto Interrupt Source Control 9 (Default: 00, R/W)) Ditto 8-13 Toshiba RISC Processor TX4939 0xE818 IC25 R/W : Type Default 2 1 ...

Page 176

... Interrupt Source Control 37 (Default: 00) Ditto Interrupt Source Control 36 (Default: 00) Ditto Interrupt Source Control 35 (Default: 00) Ditto Interrupt Source Control 34 (Default: 00) Ditto Interrupt Source Control 33 (Default: 00) Ditto Interrupt Source Control 32 (Default: 00) Ditto 8-14 Toshiba RISC Processor TX4939 0xE8C8 IC48 : Type : Default IC32 ...

Page 177

... Interrupt Source Control 45 (Default: 00) Ditto Interrupt Source Control 44 (Default: 00) Ditto Interrupt Source Control 43 (Default: 00) Ditto Interrupt Source Control 42 (Default: 00) Ditto Interrupt Source Control 41 (Default: 00) Ditto Interrupt Source Control 40 (Default: 00) Ditto 8-15 Toshiba RISC Processor TX4939 0xE8D0 Type : Default IC40 R/W : Type ...

Page 178

... Interrupt mask level 2 (Levels 3-7 enabled) 011: Interrupt mask level 3 (Levels 4-7 enabled) 100: Interrupt mask level 4 (Levels 5-7 enabled) 101: Interrupt mask level 5 (Levels 6-7 enabled) 110: Interrupt mask level 6 (Level 7 enabled) 111: Interrupt mask level 7 (Interrupts disabled) 8-16 Toshiba RISC Processor TX4939 0xE8A0 ...

Page 179

... Interrupt level 4 101: Interrupt level 5 110: Interrupt level 6 111: Interrupt level 7 Reserved Interrupt Level of INT [17] (Default: 000) Ditto Reserved Interrupt Level of INT [2] (Default: 000) Ditto Reserved Interrupt Level of INT [1] (Default: 000) Ditto7 8-17 Toshiba RISC Processor TX4939 ...

Page 180

... Edge Detection Clear Source 0 (Default: 0x0) These bits specify the interrupt source to be cleared. 1111: Reserved 0110: Reserved 0101: Reserved 0100: Interrupt Channel [5] 0011: Interrupt Channel [4] 0010: Interrupt Channel [3] 0001: Reserved 0000: Reserved 8-18 Toshiba RISC Processor TX4939 0xE8A8 EDCS1 : Type Default ...

Page 181

... IRINTREQ [11] status Ditto IRINTREQ [10] status Ditto IRINTREQ [9] status Ditto IRINTREQ [8] status Ditto IRINTREQ [7] status Ditto IRINTREQ [6] status Ditto IRINTREQ [5] status Ditto IRINTREQ [4] status Ditto IRINTREQ [3] status Ditto IRINTREQ [2] status Ditto IRINTREQ [1] status Ditto 8-19 Toshiba RISC Processor TX4939 0xE8B0 IS19 IS18 IS17 R/O R/O R/O ...

Page 182

... IRINTREQ [46] Ditto IRINTREQ [45] Ditto IRINTREQ [44] Ditto IRINTREQ [43] Ditto IRINTREQ [42] Ditto IRINTREQ [41] Ditto IRINTREQ [40] Ditto IRINTREQ [39] Ditto IRINTREQ [38] Ditto IRINTREQ [37] Ditto IRINTREQ [36] Ditto IRINTREQ [35] Ditto IRINTREQ [34] Ditto IRINTREQ [33] Ditto IRINTREQ [32] Ditto 8-20 Toshiba RISC Processor TX4939 0xE8C0 IS50 IS49 IS48 R/O R/O R/O R/O : Type 0 ...

Page 183

... Interrupt level 5 [6] 110: Interrupt level 6 [7] 111: Interrupt level 7 Reserved Interrupt Cause (Default: 0x00) These bits specify the number of original interrupt cause specified in the column "IRCS.CAUSE Bits" in Table 8-1 TX4939 Interrupt Sources. 8-21 Toshiba RISC Processor TX4939 0xE8B8 R/O : Type 1 : Default 2 1 ...

Page 184

... R/W 0x0000 Explanation Reserved Interrupt Request Flag 0 [15:0] (Default: 0x0000) Changes made to this register are reflected in Flag Register 1 also since they are the same registers. The bits in this field accept writes of both 1s and 0s. 8-22 Toshiba RISC Processor TX4939 0xE900 Type : Default ...

Page 185

... Writes to Flag Register 1 operate as follows: Write From the TX49/H4 core 1: Set the flag bit 0: No change From other devices (DMAC, PCIC) 1: Clear the flag bit 0: No change Read: Read the flag bit 8-23 Toshiba RISC Processor TX4939 0xE908 Type : Default ...

Page 186

... These bits specify the polarity of the flag bit that generated the interrupt. An interrupt request is generated when the XOR of the FPC bit and the flag bit is “1.” Flag bit (PF) FPC bit Yes 1 0 Yes 8-24 Toshiba RISC Processor TX4939 0xE910 Type : Default FPC FPC FPC [2] [1] [0] : Type ...

Page 187

... Do not reverse polarity of interrupt requests. 1: Reverse polarity of interrupt requests Internal Interrupt Polarity Control (Default: 1) This bit specifies the polarity of internal interrupt requests not reverse polarity of interrupt requests. 1: Reverse polarity of interrupt requests 8-25 Toshiba RISC Processor TX4939 0xE918 Type : Default ...

Page 188

... Reserved Internal Interrupt Mask (Default: 0x0000) These bits specify whether to use the corresponding flag bit as an internal interrupt cause. Interrupt causes are masked when this bit is “0.” 0: Mask (Reset not mask 8-26 Toshiba RISC Processor TX4939 0xE920 Type : Default ...

Page 189

... Debug Interrupt Request 0 (Default: 0x00000000) These bits are for software debug purposed only. A ‘1’ on each bit will cause the similar interrupt as in Table 8 Interrupt 1: Interrupt Note: DIR[0] and DIR[31] are not used 8-27 Toshiba RISC Processor TX4939 0xE928 ...

Page 190

... Reserved Explanation Reserved Interrupt Debug Enable (Default: 0) Enables interrupt debug registers 0: Disable Interrupt debug registers 1: Enable Interrupt debug registers 8-28 Toshiba RISC Processor TX4939 0xE8E0 DIR DIR DIR DIR [51] [50] [49] [48] : Type : Default ...

Page 191

... DMAACK[2] DMAREQ[ NAND Flash TC58DVM82F1FT00: 32MB TC58NVG1S8BFT100: 256MB 9-1 Toshiba RISC Processor TX4939 DMADONE* INT2* INT1* INT0* CE3* CE2* CE1* DMAACK[2] DMAREQ[2] DMAACK[1] DMAREQ[1] DMAACK[0] DMAREQ[0] SYSCLK BE[1] BE[0] SWE* OE* ACK* SADB[15:8] SADB[7:0] SA[5:0] SADB[15:8] SADB[7:0] ...

Page 192

... E-Bus Channel Control Register 4 (Reserved) EBCCR5 E-Bus Channel Control Register 5 (Reserved) EBCCR6 E-Bus Channel Control Register 6 (Reserved) EBCCR7 E-Bus Channel Control Register 7 (Reserved) Description Boot ROM Bus Width 16 bit 8 bit 9-2 Toshiba RISC Processor TX4939 Corresponding Register Bit CCFG.ARMODE CCFG.ACEHOLD CCFG_BESEL CCFG_ACKSEL CCFG_ROMW 9 9 ...

Page 193

... Table 9-3 Address Mask Channel Size Address Mask[35:20 0000_0000_0000_0000 2 MB 0000_0000_0000_0001 4 MB 0000_0000_0000_0011 8 MB 0000_0000_0000_0111 16 MB 0000_0000_0000_1111 32 MB 0000_0000_0001_1111 64 MB 0000_0000_0011_1111 128 MB 0000_0000_0111_1111 256 MB 0000_0000_1111_1111 512 MB 0000_0001_1111_1111 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 9-3 Toshiba RISC Processor TX4939 9 9 ...

Page 194

... Note: Address is expressed by BYTE ADDRESS accessible. Table 9-5 shows this corresponding Non-latched Lower Address Note: Address is expressed by BYTE ADDRESS 9-4 Toshiba RISC Processor TX4939 ...

Page 195

... Reserved !3f Normal Hi-Z 3f External ACK* Input ⎯ READY Input ⎯ Page Hi-Z ⎯ ⎯ Reserved 9-5 Toshiba RISC Processor TX4939 Access End G-Bus Burst Timing State Access √ Internally Generated ACK* √ ACK* Input ⎯ Ready Input √ Internally Generated ACK* ⎯ ⎯ ...

Page 196

... SADB [15:0] ACK*/READY input Figure 9-3 External ACK Mode (ACEHOLD=0) Rev. 3.1 November 1, 2005 Normal Mode (ACEHOLD= External ACK Mode (ACEHOLD= EBCCRn.SHWT=0 9-6 Toshiba RISC Processor TX4939 Rev 2. Rev 2. ...

Page 197

... Ready Mode (ACEHOLD= EBCCRn.PWT:WT=2 Page Mode (ACEHOLD= EBCCRn. PWT=1 EBCCRn. PWT=1 EBCCRn. PWT=1 Figure 9-5 Page Mode (ACEHOLD=0) 9-7 Toshiba RISC Processor TX4939 Rev 2. Rev 2. ...

Page 198

... SHWT Disable (Normal Mode, Single Read/Write Cycle, ACEHOLD= SYSCLK ACE* CE* SA [5:0] AD [28:6] OE* SWE*/BWE* SADB [15:0] ACK*/READY output Figure 9-6 SWHT Disable (Normal Mode, Single Read/Write Cycle) Rev. 3.1 November 1, 2005 9-8 Toshiba RISC Processor TX4939 EBCCRn.PWT:WT=0 EBCCRn.SHWT=0 Rev 2. ...

Page 199

... SYSCLK ACE* CE [5:0] AD [28:6] 1 OE* SWE*/BWE* SADB [15:0] ACK*/READY output Figure 9-7 SHWT 1 Wait (Normal Mode, Single Read/Write Cycle) Rev. 3.1 November 1, 2005 WRITE CYCLE 1 1 9-9 Toshiba RISC Processor TX4939 EBCCRn.PWT:WT=0 EBCCRn.SHWT=1 Rev 2. ...

Page 200

... CE* SA [5:0] AD [28:6] OE* SWE*/BWE SADB [15:0] EBCCRn.PWT:WT=2 EBCCRn.SHWT=0 ACK*/READY output Figure 9-8 ACK* Output Timing (Single Read/Write Cycle) Rev. 3.1 November 1, 2005 Single Write Cycle 1 9-10 Toshiba RISC Processor TX4939 EBCCRn.PWT:WT=2 EBCCRn.SHWT clock Rev 2. ...

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