TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 103

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

CG
5.3.5. Audio Clock Control Register
Audio Clock Generator has two registers to control. These registers are 32-bits wide. WORD accesses are allowed for
READ/WRITE (LW or SW). Those are shown Table 5-8 below.
5.3.6. MCLKOSC Register
MCLKOSC Register controls PLL set-up and configuration.
Table 5-9 describes recommended parameter values related PLL.
Following tables, i.e. Table 5-10, Table 5-11 and Figure 5-6 are describe more detail about those parameters. These values
are generated based on simulation; values are subjected to change after sample evaluation.
Rev. 3.1 November 1, 2005
Note1: Those values will be updated after ES evaluation.
Note2: Current version will not support “Simple X20, X15 PLL mode.
Fractional N PLL
Integer N PLL
Fractional N PLL
Integer N PLL
Simple X20 PLL
Simple X15 PLL
Offset Address
0xE068
0xE070
Operation Mode
FIELD Definition
FIELD Definition
FIELD Definition
FIELD Definition
MCLKOSC
MCLKOSC
MCLKOSC
MCLKOSC
DEFAULT
DEFAULT
DEFAULT
DEFAULT
R/W
R/W
R/W
R/W
20.0000 MHz
15.0000 MHz
22.5792 MHz
Definition
MCLKOSC
MCLKCTL
MSTCLK2
R/W
R/O
R/O
R/O
31
23
15
0
0
0
7
0
RESERVED
Table 5-9 Recommended Values for PLL Parameter
IS [1:0]
Figure 5-5 Definition of MCLKOSC Register
Table 5-8 Audio Clock Control Registers
Source Clock
451.584 MHz
338.688 MHz
451.584 MHz
338.688 MHz
R/W
R/O
R/O
R/O
30
22
14
0
0
0
6
0
Description
Audio Clock PLL set-up
Audio Clock Operation Control
R/W
C2S
R/W
R/O
R/O
29
21
13
0
0
0
5
1
RESERVED
MFRAC
5-9
FS [1:0]
1’b1
1’b0
1’b1
1’b0
1’b1
1’b1
R/O
R/O
R/W
R/W
28
20
12
MINTL
0
0
1
4
0
1’b1
1’b1
1’b1
1’b1
1’b0
1’b0
RESERVED
FS[1:0]
2’b00
2’b00
2’b01
2’b01
2’b00
2’b01
R/W
R/W
R/O
R/O
27
19
11
0
0
0
3
1
4’b0100
4’b0100
4’b0100
4’b0100
RS[3:0]
4’b0100
4’b0100
ND [4:0]
R/O
R/W
R/W
R/O
26
18
10
Toshiba RISC Processor
0
0
1
2
0
RS [3:0]
IS[1:0]
2’b01
2’b01
2’b01
2’b01
2’b01
2’b01
MFRAC
R/W
R/W
R/W
R/O
25
17
0
1
9
0
1
0
C2S
1’b0
1’b0
1’b1
1’b1
1’b0
1’b1
5’b00000
5’b00000
5’b00000
5’b00000
5’b10011
5’b01111
ND[4:0]
MINTL
R/W
R/W
R/W
R/O
TX4939
24
16
0
1
8
0
0
1
5
5
5
5