TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 11

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

Index
CHAPTER 17. ATA100 ATAP INTERFACE................................................................................................................... 17-1
Rev. 3.1 November 1, 2005
16.5. PCI C
16.6. A M
17.1. O
17.2. B
17.3. R
17.4. A
17.5. U
16.4.25. PCI Bus Arbiter Interrupt Mask Register (PBAMASK)............................................................................ 16-47
16.4.26. PCI Bus Arbiter Broken Master Register (PBABM) ................................................................................ 16-48
16.4.27. PCI Bus Arbiter Current Request Register (PBACREQ) ........................................................................ 16-49
16.4.28. PCI Bus Arbiter Current Grant Register (PBACGNT)............................................................................. 16-49
16.4.29. PCI Bus Arbiter Current State Register (PBACSTATE) .......................................................................... 16-50
16.4.30. G2P Memory Space 0 G-Bus Base Address Register (G2PM0GBASE)................................................ 16-51
16.4.31. G2P Memory Space 1 G-Bus Base Address Register (G2PM1GBASE)................................................ 16-52
16.4.32. G2P Memory Space 2 G-Bus Base Address Register (G2PM2GBASE)................................................ 16-53
16.4.33. G2P I/O Space G-Bus Base Address Register (G2PIOGBASE) ............................................................ 16-54
16.4.34. G2P Memory Space 0 Address Mask Register (G2PM0MASK)............................................................. 16-55
16.4.35. G2P Memory Space 1 Address Mask Register (G2PM1MASK)............................................................. 16-55
16.4.36. G2P Memory Space 2 Address Mask Register (G2PM2MASK)............................................................. 16-56
16.4.37. G2P I/O Space Address Mask Register (G2PIOMASK)......................................................................... 16-56
16.4.38. G2P Memory Space 0 PCI Base Address Register (G2PM0PBASE) .................................................... 16-57
16.4.39. G2P Memory Space 1 PCI Base Address Register (G2PM1PBASE) .................................................... 16-58
16.4.40. G2P Memory Space 2 PCI Base Address Register (G2PM2PBASE) .................................................... 16-59
16.4.41. G2P I/O Space PCI Base Address Register (G2PIOPBASE)................................................................. 16-60
16.4.42. PCI Controller Configuration Register (PCICCFG)................................................................................. 16-61
16.4.43. PCI Controller Status Register (PCICSTATUS)...................................................................................... 16-63
16.4.44. PCI Controller Interrupt Mask Register (PCICMASK) ............................................................................ 16-65
16.4.45. P2G Memory Space 0 G-Bus Base Address Register (P2GM0GBASE)................................................ 16-66
16.4.46. P2G Memory Space 1 G-Bus Base Address Register (P2GM1GBASE)................................................ 16-67
16.4.47. P2G Memory Space 2 G-Bus Base Address Register (P2GM2GBASE)................................................ 16-68
16.4.48. P2G I/O Space G-Bus Base Address Register (P2GIOGBASE)............................................................ 16-69
16.4.49. G2P Configuration Address Register(G2PCFGADRS) .......................................................................... 16-70
16.4.50. G2P Configuration Data Register (G2PCFGDATA)................................................................................ 16-71
16.4.51. G2P Interrupt Acknowledge Data Register (G2PINTACK) ..................................................................... 16-72
16.4.52. G2P Special Cycle Data Register (G2PSPC)......................................................................................... 16-72
16.4.53. Configuration Data 0 Register (PCICDATA0) ......................................................................................... 16-73
16.4.54. Configuration Data 1 Register (PCICDATA1) ......................................................................................... 16-73
16.4.55. Configuration Data 2 Register (PCICDATA2) ......................................................................................... 16-74
16.4.56. Configuration Data 3 Register (PCICDATA3) ......................................................................................... 16-74
16.4.57. PDMAC Chain Address Register (PDMCA) ........................................................................................... 16-75
16.4.58. PDMAC G-Bus Address Register (PDMGA) .......................................................................................... 16-76
16.4.59. PDMAC PCI Bus Address Register (PDMPA) ........................................................................................ 16-77
16.4.60. PDMAC Count Register (PDMCTR)....................................................................................................... 16-78
16.4.61. PDMAC Control Register (PDMCFG) .................................................................................................... 16-79
16.4.62. PDMAC Status Register (PDMSTATUS) ................................................................................................ 16-81
16.5.1. Configuration Space Register Map .......................................................................................................... 16-84
16.5.2. Memory Space (m) Lower Base Address (m=0, 1, 2) .............................................................................. 16-85
16.5.3. IO Space Base Address (24h).................................................................................................................. 16-86
16.5.4. Capability ID Register (Cap_ID)
16.5.5. Next Item Pointer Register (Next_Item_Ptr)
16.5.6. Power Management Capability Register (PMC)
16.5.7. Power Management Control/Status Register (PMCSR)
16.6.1. Outline of the problem.............................................................................................................................. 16-89
16.6.2. Condition of the problem occurrence ....................................................................................................... 16-89
16.6.3. Work-around ............................................................................................................................................ 16-89
17.3.1. Register address map ................................................................................................................................ 17-3
17.3.2. Registers in slave mapping ........................................................................................................................ 17-5
17.3.3. ATA100 Core Control Registers ............................................................................................................... 17-12
17.4.1. Data transfer in the PIO mode ................................................................................................................. 17-24
17.4.2. Multiword DMA mode data transfer .......................................................................................................... 17-27
17.5.1. When a read command is issued to the device (transfer start position) ................................................... 17-29
17.5.2. When read command is issued to the device (Transfer End Position) ..................................................... 17-31
17.5.3. When Write Command is issued to the device (Transfer Start Position) .................................................. 17-32
17.5.4. When Write Command is issued to the device (Transfer End Position) ................................................... 17-33
LOCK
CTUAL
EGISTER
LTRA
VERVIEW
ALFUNCTION OF
ONFIGURATION
DMA
D
O
IAGRAM
PERATION
........................................................................................................................................................... 17-1
L
IST
MODE DATA TRANSFER
.................................................................................................................................................... 17-3
.................................................................................................................................................. 17-2
PCI C
T
S
IMING
PACE
ONTROLLER
................................................................................................................................ 17-24
R
EGISTER
...................................................................................................................... 17-29
................................................................................................................. 16-89
................................................................................................................ 16-84
0xDC ................................................................................................. 16-86
vii
0xDD .............................................................................. 16-86
0xDE ......................................................................... 16-87
0xE0 .............................................................. 16-88
Toshiba RISC Processor
TX4939