TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 113

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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Address
6.3. DDR SDRAM Mapping
6.3.1. Fundamentals
The DDR SDRAM Controller in TX4939 can support 1.0 GB memory capacity per channel. As this size exceeds the size of
kseg0 and kseg1 (which size is 512 MB), there might be an issue to map this whole memory to the physical address
0x0_0000_0000.
The DDR SDRAM Mapping logic will provide system with the capability to split such DDR memory space exceed 512 MB to
smaller region and map to any region of physical address space.
The granularity is intended to be 16 MB as target. However, it may increase if there are timing issues in the implementation.
Also, to avoid design complexity, the maximum window size is 1.0 GB and window across the 1.0 GB boundary is prohibited.
6.3.2. Control Registers
Table 6-1 shows the registers for DDR Memory Mapping Control.
Use Double Word (LD/SD) or Word (LW/SW) load/store to access register.
Rev. 3.1 November 1, 2005
0x8200
0x8208
0x8210
0x8218
0x8220
LD/SD
LE/BE
Offset Address
LW/SW
0x820C
0x821C
0x8200
0x8204
0x8208
0x8210
0x8214
0x8218
0x8220
0x8224
LE/BE
Table 6-1 Internal Registers for DDR SDRAM Mapping Control
Register Size (bit)
64
64
64
64
64
DDR SDRAM Memory Mapping Control Register
Register Symbol
DRWINEN
DRWIN00
DRWIN01
DRWIN02
DRWIN03
6-3
Enable/Disable DDR Mapping Windows
DDR Mapping Window #0
DDR Mapping Window #1
DDR Mapping Window #2
DDR Mapping Window #3
Register Name
Toshiba RISC Processor
TX4939
6
6

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