TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 144

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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Configuration
Rev. 3.1 November 1, 2005
3
2
1
0
Bit
---
ENDIAN
ARMODE
ACEHOLD
Mnemonic
Reserved
Endian
ACK*/READY
Mode
ACE Hold
Field Name
Table 7-2 Chip Configuration Register
---
Indicates the TX4939 Endian mode setting.
0 = Little Endian mode
1 = Big Endian mode
Selects an ACK*/READY signal operation mode for the
external bus controller (refer to Section 7.3.6).
0 = ACK*/READY dynamic mode
1 = ACK*/READY static mode
Specifies the hold time of an address relative to the external
bus controller ACE* signal (refer to Section 7.3.4).
0 = Switch the address at the same time when the ACE*
signal is deasserted.
1 = Switch the address one clock cycle after the ACE* signal
is deasserted.
7-6
Description
Toshiba RISC Processor
---
SADB[4]
0
1
Initial Value
R/O
R/O
R/W
R/W
TX4939
R/W
7
7

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