TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 147

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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Configuration
Rev. 3.1 November 1, 2005
63:62
61
60
59:58
57
56:51
50
49:46
45:44
43
42
41
40
39:33
32
31:28
27
26:20
19
18
17
16
Bit
SIO2MODE[1:
0]
SPIMODE
I2CMODE
I2SMODE
SIO3MODE
DMASEL3
VSSMODE,V
PSMODE
ET1MODE
ET0MODE
ATA1MODE
ATA0MODE
BP_PLL
SYSCLKEN
PCICLKEN[4]
PCICLKEN[3]
PCICLKEN[2]
PCICLKEN[1]
Mnemonic
Setting of
shared pins
Setting of
shared pin
Setting of
shared pin
Setting of
shared pin
Setting of
shared pin
Reserved
DMA Request
Select 3
Reserved
Setting of
shared pin
Setting of
shared pin
Setting of
shared pin
Setting of
shared pin
Setting of
shared pin
Reserved
Bypass PLL
Reserved
SYSCLK
Enable
Reserved
PCICLK4
Enable
PCICLK3
Enable
PCICLK2
Enable
PCICLK1
Enable
Field Name
Table 7-4 Pin Configuration Register
SIO2 Shared-pin setting
1x: GPIO Mode (GPIO12, GPIO13)
01: SIO2 Mode (GPIO12 = RXD2, GPIO13 = TXD2)
00: SIO0 Mode (GPIO12 = CTS0, GPIO13 = RTS0)
SPI Shared-pin setting
1: SIO/GPIO Mode
0: SPI Mode
I2C Shared-pin setting
1 : I2C Mode
0 : GPIO Mode
I2S Shared-pin setting
11 : GPIO Mode
10 : I2S Mode
01 : I2S Mode
00 : ACLC Mode
SIO3 Shared-pin setting
1 : GPIO Mode
0 : SIO Mode
Used only when SPIMODE = 1
Selects a DMA request used by DMA controller 0 channel 3.
0: NDFC
1: SIO channel 0 transmission
Video Port Shared-pin setting
{PTSEL,VSSMODE,VPSMODE}
000 : All GPIO
001 : 1-Parallel ports and GPIO
010 : 3-Serial port and GPIO
011 : 1-Parallel and 1-Serial port
1xx : PC Trace Mode
Please refer to Table3-8 in Chapter 3
Ethernet MAC1 Shared-pin setting
1 : MAC1 Mode
0 : Other Mode
Please refer to Table3-7 in Chapter 3
Ethernet MAC0 Shared-pin setting
1 : MAC0 Mode
0 : Other Mode
Please refer to Table3-7 in Chapter 3
ATA1 Shared-pin setting
1 : ATA1 Mode
0 : Other Mode
Please refer to Table3-7 in Chapter 3
ATA0 Shared-pin setting
1 : ATA0 Mode
0 : GPIO Mode
Indicates information about whether internal PLLs are on or
off.
1 = The PLL is on
0 = The PLL is off..
Specifies whether to output the SYSCLK.
1 = Clock output
0 = Tri-state
PCICLK4 Enable
0: IOSRST*
1: Clock output
PCICLK3 Enable
0: SYSRST*
1: Clock output
PCICLK2 Enable
0: L
1: Clock output
PCICLK1 Enable
0: L
1: Clock output
7-9
Description
Toshiba RISC Processor
11
1
0
11
1
1
00
0
0
0
0
BYPASSPLL*
1
0
0
0
1
Initial Value
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
TX4939
R/W
7
7

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