TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 150

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

Configuration
7.2.5. Clock Control Register (CLKCTR)
For the low-order 19 bits of the clock control register, canceling a reset requires that the corresponding reset bit be cleared
by software. Before clearing them, wait at least 128 CPU clock cycles after they are set.
Rev. 3.1 November 1, 2005
DMA0CKD
DMA0RST
SIO1CKD
SIO1RST
I2CCKD
IOSRST
I2CRST
R/W
R/W
R/W
R/W
R/W
R/W
R/W
63
55
47
39
31
23
15
0
0
0
0
0
0
7
0
RESERVED
ETH0CKD
ETH0RST
PCICCKD
PCICRST
VPCCKD
VPCRST
SYSRST
R/W
R/W
R/W
R/W
R/W
R/W
R/W
62
54
46
38
30
22
14
0
0
0
0
0
0
6
0
EPCIRST
TM5CKD
TM5RST
SPICKD
I2SCKD
SPIRST
I2SRST
R/W
R/W
R/W
R/W
R/W
R/W
61
53
45
37
29
21
13
0
0
0
0
0
5
0
RESERVED
RESERVED
SRAMCKD
SRAMRST
Figure 7-5 Clock Control Register
TM4CKD
TM0CKD
TM4RST
TM0RST
R/W
R/W
R/W
R/W
R/W
60
52
44
36
28
20
12
0
0
0
0
4
0
ETH1CKD
ETH1RST
PCI1CKD
PCI1RST
TM3CKD
TM1CKD
TM3RST
TM1RST
7-12
R/W
R/W
R/W
R/W
R/W
R/W
R/W
59
51
43
35
27
19
11
0
0
0
0
0
1
3
0
DMA1CKD
DMA1RST
ATA1CKD
ATA1RST
TM2CKD
TM2RST
CIRCKD
CIRRST
R/W
R/W
R/W
R/W
R/W
R/W
R/W
58
50
42
34
26
18
10
0
0
0
0
0
0
2
0
BROMCKD
BROMRST
SIO3CKD
SIO0CKD
SIO3RST
SIO0RST
ACLCKD
ACLRST
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
57
49
41
33
25
17
0
0
0
0
0
0
9
0
1
0
Toshiba RISC Processor
ATA0CKD
ATA0RST
SIO2CKD
NDCCKD
SIO2RST
CYPCKD
NDCRST
CYPRST
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
56
48
40
32
24
16
0
0
0
0
0
0
8
0
0
0
0xE020
: Default
: Default
: Default
: Default
: Default
: Default
: Default
: Default
: R/W
: R/W
: R/W
: R/W
: R/W
: R/W
: R/W
: R/W
TX4939
7
7