TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 154

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

Configuration
7.2.6. G-Bus Arbiter Control Register (GARBC)
Rev. 3.1 November 1, 2005
63
62:36
35:0
ARBM
R/W
Bit
63
47
31
15
D
1
PRIORITY
PRIORITY
62
46
30
14
ARBMD
⎯
PRIORITY
Mnemonic
L7[3:0]
L3[3:0]
61
45
29
13
60
44
28
12
Arbitration
Mode
Reserved
Arbitration
Priority
Field Name
59
43
27
11
RESERVED
PRIORITY
PRIORITY
58
42
26
10
L6[3:0]
L2[3:0]
Figure 7-6 G-Bus Arbiter Control Register
Table 7-7 G-Bus Arbiter Control Register
Specifies how to prioritize G-Bus arbitration.
0 = Fixed priority. The G-Bus arbitration priority conforms to
the content of the PRIORITY field (bits [23:0]).
1 = Round-robin (in a round-robin fashion, PCIC0 > PDMAC
> DMAC0 > DMAC1 > PCIC1 > ATA0 > ATA1 > CYP > VPC)
Note: Before accessing the PCI by DMAC, specify
round-robin as the priority mode. If fixed-priority mode is
selected, a dead lock is likely to occur in PCI bus
access.
⎯
Specifies the priority when ARBMD (bit [63]) specifies
fixed-priority mode.
[35:32] = Bus master with the highest priority
[31:28] = Bus master with the second highest priority
[27:24] = Bus master with the third highest priority
[23:20] = Bus master with the fourth highest priority
[19:16] = Bus master with the fifth highest priority
[15:12] = Bus master with the sixth highest priority
[11:8] = Bus master with the seventh highest priority
[7:4] = Bus master with the eighth highest priority
[3:0] = Bus master with the ninth highest priority
The 3-bit codes for different Masters are:
0000 = PCI controller
0001 = PDMAC
0010 = DMAC0
0011 = DMAC1
0100 = PCI controller 1
0101 = ATA0
0110 = ATA1
0111 = CYP
1000 = VPC controller
A priority of PCIC > PDMAC > DMAC0 > DMAC1 > PCIC1 >
ATA0 > ATA1 > CYP > VPC is initially set up.
57
41
25
9
56
40
24
8
RESERVED
55
39
23
7-16
7
Description
PRIORITY
PRIORITY
54
38
22
6
L5[3:0]
L1[3:0]
53
37
21
5
52
36
20
4
51
35
19
3
PRIORITY
PRIORITY
PRIORITY
50
34
18
2
L8[3:0]
L4[3:0]
L0[3:0]
Toshiba RISC Processor
49
33
17
1
1
⎯
0000_0001_
0010_0011_
0100_0101_
0110_0111_
1000
Initial Value
0xE030
48
32
16
0
: Default
: Default
: Default
: Default
: R/W
: R/W
: R/W
: R/W
TX4939
⎯
R/W
R/W
R/W
7
7