TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 156

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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Configuration
7.2.8. DLL De-Skew Control Register (DSKWCTRL)
This register controls the enabling of the locking mechanism for the PCI & DDR DLLs. This register’s bits also control what
kind of control signal to be used for enabling the DLL locking.
Rev. 3.1 November 1, 2005
63
47
31
15
63:10
9:8
7:0
Bit
62
46
30
14
DDRDSKW
Mnemonic
RESERVED
61
45
29
13
60
44
28
12
Reserved
DDR DLL
De-Skew
Enable
Reserved
59
43
27
11
Field Name
58
42
26
10
DDRDSKW
57
41
25
Figure 7-8 DLL De-Skew Control Register
9
Table 7-9 DLL De-Skew Control Register
2'b11
Controls enabling of DDR DLL Locking.
2’b00 = Disable DLL Locking and force zero delay.
2’b01 = Reserved
2’b10 = Reserved
2’b11 = Always Enable Locking.
R/W
56
40
24
8
RESERVED
RESERVED
RESERVED
55
39
23
7
7-18
Description
54
38
22
6
RESERVED
53
37
21
5
52
36
20
4
51
35
19
3
50
34
18
2
Toshiba RISC Processor
49
33
17
1
2’b11
Initial Value
0xE060
48
32
16
0
: Default
: Default
: Default
: Default
TX4939
: R/W
: R/W
: R/W
: R/W
R/W
R/W
7
7

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