TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 16

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

Index
List of Figures
Rev. 3.1 November 1, 2005
Figure 1-1 System Block Diagram ........................................................................................................................... 1-2
Figure 1-2 Two ATA100 for DVD Recorder .............................................................................................................. 1-3
Figure 1-3 One ATA100 and Two Ethernet System ................................................................................................. 1-4
Figure 2-1 TX4939 Internal Block Diagram.............................................................................................................. 2-1
Figure 3-1 Pin Assignment on Package (TOP VIEW) .............................................................................................. 3-4
Figure 4-1 Boot Configuration Settling Timing ......................................................................................................... 4-1
Figure 5-1 Overview of Clocking System in TX4939 ............................................................................................... 5-1
Figure 5-2 Master Clock Generator ......................................................................................................................... 5-2
Figure 5-3 Diagram of Audio Clock Generator......................................................................................................... 5-3
Figure 5-4 Block Diagram of Fractional N PLL ........................................................................................................ 5-5
Figure 5-5 Definition of MCLKOSC Register ........................................................................................................... 5-9
Figure 5-6 Frequency Selection related to FS[1:0] and C2S value........................................................................ 5-10
Figure 5-7 Definition of MCLKCTL Register ...........................................................................................................5-11
Figure 5-8 Location of SSCG UNIT ....................................................................................................................... 5-13
Figure 5-9 Concept of Clock De-Skew Circuit ....................................................................................................... 5-14
Figure 5-10 Structure of DDR Clock De-Skew Circuit............................................................................................ 5-14
Figure 5-11 Structure of PCI Clock De-Skew Circuit.............................................................................................. 5-15
Figure 6-1 Logical to Physical Address Translation ................................................................................................. 6-1
Figure 6-2 Physical Address Map at Initializing System .......................................................................................... 6-2
Figure 6-3 DDR Mapping Window Control .............................................................................................................. 6-4
Figure 6-4 DDR Mapping Window Control .............................................................................................................. 6-5
Figure 6-5 Example of DDR Memory Split-Mapping ................................................................................................ 6-6
Figure 6-6 P2G Memory Space (n) PCI Lower Address Register ............................................................................ 6-7
Figure 6-7 Generating Physical Address for a Internal Register .............................................................................. 6-9
Figure 7-1 Chip Configuration Register ................................................................................................................... 7-3
Figure 7-2 Chip Revision ID Register ...................................................................................................................... 7-7
Figure 7-3 Pin Configuration Register ..................................................................................................................... 7-8
Figure 7-4 Timeout Error Access Register ..............................................................................................................7-11
Figure 7-5 Clock Control Register ......................................................................................................................... 7-12
Figure 7-6 G-Bus Arbiter Control Register ............................................................................................................. 7-16
Figure 7-7 Register Address Mapping Register ..................................................................................................... 7-17
Figure 7-8 DLL De-Skew Control Register ............................................................................................................ 7-18
Figure 7-9 Definition of MCLKOSC Register ......................................................................................................... 7-19
Figure 7-10 Definition of MCLKCTL Register ........................................................................................................ 7-20
Figure 7-11 GPIOMR1 Register............................................................................................................................. 7-21
Figure 7-12 GPIODR1 Register............................................................................................................................. 7-22
Figure 7-13 GPIOMR2 Register ............................................................................................................................ 7-23
Figure 7-14 GPIODR2 Register............................................................................................................................. 7-24
Figure 8-1 Interrupt Controller Outline ..................................................................................................................... 8-2
Figure 8-2 Internal Block Diagram of Interrupt Controller ........................................................................................ 8-3
Figure 8-3 External Interrupt Request Logic ........................................................................................................... 8-8
Figure 8-4 Interrupt Detection Enable Register ..................................................................................................... 8-10
Figure 8-5 Interrupt Source and Cause IP Binding Register...................................................................................8-11
Figure 8-6 Interrupt Detection Mode Register 0..................................................................................................... 8-12
Figure 8-7 Interrupt Detection Mode Register 1..................................................................................................... 8-13
Figure 8-8 Interrupt Detection Mode Register 2..................................................................................................... 8-14
Figure 8-9 Interrupt Detection Mode Register 3..................................................................................................... 8-15
Figure 8-10 Interrupt Mask Level Register ............................................................................................................ 8-16
Figure 8-11 Interrupt Level Registers .................................................................................................................... 8-17
Figure 8-12 Interrupt Edge Detection Clear Register............................................................................................. 8-18
Figure 8-13 Interrupt Pending Register 0 .............................................................................................................. 8-19
Figure 8-14 Interrupt Pending Register 1 .............................................................................................................. 8-20
Figure 8-15 Interrupt Current Status Register........................................................................................................ 8-21
Figure 8-16 Interrupt Request Flag Register 0 ...................................................................................................... 8-22
Figure 8-17 Interrupt Request Flag Register 1 ...................................................................................................... 8-23
Figure 8-18 Interrupt Requests Polarity Control Register ...................................................................................... 8-24
Figure 8-19 Interrupt Request Control Register..................................................................................................... 8-25
Figure 8-20 Interrupt Request Internal Interrupt Mask Register............................................................................. 8-26
Figure 8-21 Interrupt Request External Interrupt Mask Register ........................................................................... 8-27
Figure 8-22 Interrupt Debug Register 0 ................................................................................................................. 8-27
Figure 8-23 Interrupt Debug Register 1 ................................................................................................................. 8-28
Figure 8-24 Interrupt Debug Enable Register ........................................................................................................ 8-28
Figure 9-1 External Circuit for External Bus Interface for 8/16-bit mode.................................................................. 9-1
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Toshiba RISC Processor
TX4939