TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 169

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

INTC
8.3.8. Interrupt Notification of Original Mode
When the interrupt with the highest priority is selected, then the interrupt factor is reported to the Interrupt Current Status
Register (IRCS) and an interrupt is reported to the TX49/H4 core.
Any interrupt occurrence will assert CP0.IP[2] bit. When IP[2] has value one IP[7:3] will show the interrupt source number
described in Table 8-3 column of IP[7:3]. This value has meaning only when the internal timer interrupt is disabled. Since
IP[7:3] is 5 digit binary, the interrupt that number is more than 31 will appear as 31. In this case, interrupt handler should
refer the content of IRCS.CAUSE register.
The internal timer interrupt can be disable by setting TINTDIS. This value can be set at the boot time also.
See more detail “Chapter 5 Boot Configuration”.
8.3.9. Interrupt Notification of Compatible Mode
Any interrupt occurrence will be informed to CP0 IP[2] same as former TX49 Series, i.e. TX4938.
However, the usage of IP[7:3] has been changed as follows.
IP[7] will be use for Internal timer interrupt exclusively.
IP[6:3] will not get the part of IRCS.CAUSE register instead it will used for selected interrupt indication. (See more detail in
8.4.2 Interrupt Source and Cause IP Binding Register (ISCIPB))
8.3.10. Clearing Interrupt Requests
Interrupt requests are cleared according to the following process.
Rev. 3.1 November 1, 2005
TINTDIS
0 : Internal Timer Interrupts:
1 : Internal Timer Interrupts:
TINTDIS
0 : Internal Timer Interrupts:
1 : Internal Timer Interrupts:
When the detection mode is set to the High level or Low level:
□ Operation is performed to de-assert the request of a source that is asserting an interrupt request.
When the detection mode is set to Rising edge or Falling edge
□ Edge detection requests are cleared by first specifying the interrupt source of the interrupt request to be
Valid
Invalid
Valid
Invalid
cleared in the Edge Detection Clear Source field (EDCS0 or EDCS1) of the Interrupt Edge Detection Clear
Register (IREDC) then writing the resulting value when the corresponding Edge Detection Clear Enable bit
(EDCE0 or EDCE1) is set to “1.”
Table 8-3 Interrupt Notification to IP[7:2] of the CP0 Cause Register
Table 8-4 Interrupt Notification to IP[7:2] of the CP0 Cause Register
IP[7]
Internal Timer
Interrupt
Notification
Note: IRCS.CAUSE value never takes 31 by design.
IP[7]
Internal Timer Interrupt
Notification
No Internal Timer Interrupt
Notification
If IRCS.CAUSE < 31, CP0 IP[7:3] <= (IRCS.CAUSE)
If IRCS.CAUSE > 31, CP0 IP[7:3] <= 31
IP[6:3]
LOGICALLY, THIS DOES NOT HAVE MUCH MEANING.
If IRCS.CAUSE < 31, CP0 IP[6:3] <= 0x0F && (IRCS.CAUSE)
If IRCS.CAUSE > 31, CP0 IP[6:3] <= 15
IP[6:3]
Indicate occurrence of selected interrupt
Indicate occurrence of selected interrupt
8-7
Toshiba RISC Processor
IP[2]
Indicate
occurrence of
any interrupt
Indicate
occurrence of
any interrupt
IP[2]
Indicate
occurrence of
any interrupt
Indicate
occurrence of
any interrupt
TX4939
8
8