TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 170

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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8.3.11. Interrupt requests
It is possible to make interrupt requests to external devices and interrupt requests (IRC interrupts) to the TX49/H4 core by
using a 16-bit interrupt request flag register. REQ[1]* signals are used as interrupt output signals. Consequently, external
interrupt requests can only be used when in the PCI External Arbiter mode. Also, internal interrupt requests are assigned to
interrupt number 14 of the Interrupt Controller (IRC).
The following six registers set the interrupts.
The following formulas derive the interrupt generation conditions:
Internal interrupt request =
External interrupt request =
In the above formulas, “^” indicates Exclusive OR operations and “|” indicates reduction operators that perform an OR
operation on all bits.
Also, the External Interrupt OD Control bit (IRRCNT.OD) of the Interrupt Request Control Register can select whether the
external interrupt supply signal is open drain output or totem pole output.
There are two flag registers: Flag Register 0 (IRFLAG0), and Flag Register 1 (IRFLAG1). These registers have two different
Write methods. Accordingly, Writes to one register are reflects in the other.
In the case of Flag Register 1 however, “1” can be written from the TX49/H4 core, but “0” cannot be written. On the other
hand, bits that wrote “1” are cleared to “0” in the case of access from a device other than the TX49/H4 core (access from an
external PCI device for example). The bit value at this time will not change even if “0” is written. This register sends
interrupt notification from the TX49/H4 core to external devices. External devices can be used in applications that clear
these interrupt notifications.
Rev. 3.1 November 1, 2005
Interrupt Request Flag Register (IRFLAG0, IRFLAG1)
Interrupt Request Polarity Control Register (IRPOL)
Interrupt Request Mask Register (IRMASKINT, IRMASKEXT)
Interrupt Request Control Register (IRRCNT)
(|((IRFLAG[15:0] ^ IRPOL[15:0]) & IRMASKINT[15:0]))^ IRRCNT.INTPOL
(|((IRFLAG[15:0] ^ IRPOL[15:0] ) & IRMASKEXT[15:0]))^ IRRCNT.EXTPOL
Either “0” or “1” can be written to Flag Register 0
IRRCNT.EXTPOL
IRRCNT.INTPOL
IRMASK[15]
IRFLAG[15]
IRPOL[15]
Figure 8-3 External Interrupt Request Logic
8-8
Internal Interrupt
Request
(0: Request present)
External Interrupt Request
Toshiba RISC Processor
TX4939
8
8

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