TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 187

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

INTC
8.4.16. Interrupt Request Control Register (IRRCNT)
Rev. 3.1 November 1, 2005
Bit
31:3
2
1
0
31
15
30
14
Mnemonic
⎯
ODC
EXTPOL
INTPOL
29
13
28
12
27
11
Field Name
⎯
External Interrupt
OD Control
External Interrupt
Request Polarity
Control
Internal Interrupt
Request Polarity
Control
Figure 8-19 Interrupt Request Control Register
Table 8-21 Interrupt Request Control Register
26
10
RESERVED
25
9
RESERVED
24
8
Explanation
Reserved
External Interrupt Open Drain Control (Default: 0)
This bit specifies whether to make the external interrupt signal
(IRC[2]*) an open drain pin or not.
0: Open drain (reset)
1: Totem pole
External Interrupt Polarity Control (Default: 1)
This bit specifies the polarity of external interrupt requests.
0: Do not reverse polarity of interrupt requests.
1: Reverse polarity of interrupt requests
Internal Interrupt Polarity Control (Default: 1)
This bit specifies the polarity of internal interrupt requests.
0: Do not reverse polarity of interrupt requests.
1: Reverse polarity of interrupt requests
8-25
23
7
22
6
21
5
20
4
19
3
ODC EXTPOL INTPOL
R/W
18
2
0
Toshiba RISC Processor
R/W
17
1
1
0xE918
R/W
16
0
1
: Default
: Default
: Type
: Type
R/W
⎯
R/W
R/W
R/W
TX4939
8
8