TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 190

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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8.4.20. Interrupt Debug Register 1 (IRDBR1)
8.4.21. Interrupt Debug Enable Register (IRDBEN)
Rev. 3.1 November 1, 2005
Bit
31:0
DIR
DIR
[63]
[47]
31
15
31
15
Bit(s)
31:1
0
DIR
[62]
DIR
[46]
30
14
30
14
Mnemonic
DIR [63:32]
Mnemonic
IRDBEN
DIR
[61]
DIR
[45]
29
13
29
13
DIR
[60]
DIR
[44]
28
12
28
12
DIR
[59]
DIR
[43]
27
11
27
11
Field Name
Debug Interrupt
Request
Field Name
Interrupt Debug
Enable
DIR
[58]
DIR
[42]
Figure 8-24 Interrupt Debug Enable Register
26
10
26
10
Table 8-26 Interrupt Debug Enable Register
Figure 8-23 Interrupt Debug Register 1
Table 8-25 Interrupt Debug Register 1
DIR
[57]
DIR
[41]
25
25
9
9
DIR
[56]
DIR
[40]
24
Explanation
Debug Interrupt Request 1(Default: 0x00000000)
These bits are for software debug purposed only. A ‘1’ on each
bit will cause the similar interrupt as in Table 8-1
0: No Interrupt
1: Interrupt
Note: DIR[63:51], DIR[35], and DIR[32] are not used
24
Reserved
8
8
0x0000
0x0000
R/W
R/W
Explanation
Reserved
Interrupt Debug Enable (Default: 0)
Enables interrupt debug registers
0: Disable Interrupt debug registers
1: Enable Interrupt debug registers
DIR
DIR
[55]
[39]
8-28
23
23
7
7
DIR
DIR
[54]
[38]
22
22
6
6
DIR
[53]
DIR
[37]
21
21
5
5
DIR
[52]
DIR
[36]
20
20
4
4
DIR
[51]
DIR
[35]
19
19
3
3
DIR
[50]
DIR
[34]
18
18
2
2
Toshiba RISC Processor
DIR
[49]
DIR
[33]
17
17
1
1
IRDB
0xE8E0
0xE8E8
R/W
DIR
[48]
DIR
[32]
EN
16
16
0
0
0
R/W
R/W
: Default
: Default
: Default
: Default
R/W
R/W
: Type
: Type
: Type
: Type
TX4939
8
8

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