TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 192

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

EBC
9.2.
9.2.1.
The External Bus Controller (EBC) has four (4) independent channels. Each channel has own Channel Control Register
(EBCCRn: n=0-3),that can be configured separately. Table 9-1 is the list of these registers. The channel 0 is dedicated for
boot device.
These control registers can be accessed either WORD or DWORD; however, EBCCRn.ME bit should be enabled at the last
timing of WORD access. Otherwise, undesirable memory access may happen.
9.2.2.
Since EBCCR0 is dedicated for boot device, EBCCR0 is set enable as boot channel. (EBCCR0.ME = 1'b1)
Rev. 3.1 November 1, 2005
NO PIN
ASSIGNED
NO PIN
ASSIGNED
SADB[1]
SADB[2]
SADB[3]
Signal
External Bus Controller
External Bus Channel Control Registers
Boot Up Options
ADDRESS
Table 9-2 Boot Configuration for Channel 0 (Subset of Table 4-1 Boot Configuration Details)
OFFSET
0x9000
0x9008
0x9010
0x9018
0x9020
0x9028
0x9030
0x9038
Selects the operation mode of the ACK*/READY signal.
1 = ACK*/READY Static mode
0 = ACK*/READY Dynamic mode (Default)
Set the address hold time relative to the ACE* signal.
1 = Address changes 1 clock cycle after deassertion of the ACE* signal (Default)
Specifies the function of the BE[1:0]*/BWE[1:0]* pins upon booting.
1 = BWE[3:0]* (Byte Write Enable)
0 = BE[3:0]* (Byte Enable)
Boot ACK* Input : Specifies the access mode for external bus controller channel 0.
1 = Normal mode
0 = External ACK mode
Boot ROM Bus Width. Specifies the data bus width when booting from a memory device
connected to the External bus controller.
BIT WIDTH
64
64
64
64
64
64
64
64
SADB [3]
0
1
Table 9-1 External Bus Control Registers
EBCCR0
EBCCR1
EBCCR2
EBCCR3
EBCCR4
EBCCR5
EBCCR6
EBCCR7
REGISTER
SYMBOL
Description
Boot ROM Bus Width
16 bit
8 bit
9-2
E-Bus Channel Control Register 0 (Boot Device)
E-Bus Channel Control Register 1
E-Bus Channel Control Register 2
E-Bus Channel Control Register 3
E-Bus Channel Control Register 4 (Reserved)
E-Bus Channel Control Register 5 (Reserved)
E-Bus Channel Control Register 6 (Reserved)
E-Bus Channel Control Register 7 (Reserved)
REGISTER NAME
Toshiba RISC Processor
CCFG.ARMODE
CCFG.ACEHOLD
CCFG_BESEL
CCFG_ACKSEL
CCFG_ROMW
Corresponding
Register Bit
TX4939
9
9