TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 198

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

EBC
9.2.8.
9.2.8.1.
The SHWT option is selected when the SHWT (Setup/Hold Wait Time) field of the Channel Control Register is a value other
than “0.” This option inserts a Setup cycle and a Hold cycle between the current signal and the next signal.
Setup cycle:
Hold cycle:
This option is used for I/O devices that are generally slow. All Setup cycles and Hold cycles will be identical, so each cycle
cannot be set individually. The SHWT mode cannot be used by the Page mode. The SHWT mode can be used by all other
modes, but there is one restriction: the internal bus cannot use Burst access.
The hold cycles of SADB relative to SWE* and BWE* are fixed at one clock cycle, regardless of setting of the SHWT option.
When the SHWT option is disabled, the setup cycles of SWE* and BWE* relative to CE*, and the hold cycles of SWE*and
BWE* relative to CE* are one clock cycle.
Rev. 3.1 November 1, 2005
ACK*/READY
SWE*/BWE*
SADB [15:0]
AD [28:6]
SYSCLK
SA [5:0]
Access Timing
output
SHWT Option
ACE*
OE*
CE*
CE* from ADDR, OE* from CE*, BWE* from CE*, SWE* from CE*.
ADDR from CE*, CE* from OE*, CE* from BWE*, CE* from SWE*
0
SHWT Disable (Normal Mode, Single Read/Write Cycle, ACEHOLD=0)
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Figure 9-6 SWHT Disable (Normal Mode, Single Read/Write Cycle)
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EBCCRn.PWT:WT=0
EBCCRn.SHWT=0
Toshiba RISC Processor
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TX4939
Rev 2.13
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