TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 207

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

EBC
Rev. 3.1 November 1, 2005
Bit
11:8
7
6
5:4
3
2:0
Mnemonic
CS
BC
RDY
SP
ME
SHWT
Field Name
Channel Size
Byte Control
Ready Input Mode
BOOTSP
Master Enable
Set Up/Hold
Time
Table 9-8 External Bus Channel Control Register
Wait
Description
External Bus Control Channel Size (Default: 0010/0000)
Specifies the channel memory size.
0000: 1 MB
0001: 2 MB
0010: 4 MB
0011: 8 MB
0100: 16 MB
0101: 32 MB
0110: 64 MB
0111: 128 MB
1000: 256 MB
1001: 512 MB
1010 – 1111: Reserved
*
the memory bus width is 16 bits, or up to 256 MB when the memory
bus width is 8 bits. No size larger than this can be set.
External Bus Byte Control (Default:SADB[1]/0)
Specifies whether to use the BWE*[1:0] signal as an asserted Byte
Write Enable signal (BWE*[1:0]) only during a Write cycle, or to use it
as an asserted Byte Enable signal (BE*[1:0]) that is asserted during
both Read and Write cycles.
0: Byte Enable (BE *[1:0])
1: Byte Write Enable (BWE*[1:0])
Note: SADB[1] is set to Channel 0 as the default.
External Bus Control Ready Input Mode (Default: 0)
Specifies whether to use the Ready mode.
0: Disable the Ready mode.
1: Enable the Ready mode.
Note: The Ready mode cannot be used when the Page mode is
selected.
External Bus Control Bus Speed (Default: SA[4:3] / 00)
Specifies the External Bus speed.
00: 1/4 speed (1/4 of the GBUSCLK frequency)
01: 1/3 speed (1/3 of the GBUSCLK frequency)
10: 1/5 speed (1/5 of the GBUSCLK frequency)
11: 1/6 speed (1/6 of the GBUSCLK frequency)
External Bus Control Master Enable (Default: 1 / 0)
Enables a channel.
0: Disable channel
1: Enable channel
Note: set to 1 for Channel 0 as the default.
External Bus Control Setup/Hold Wait Time (Default: 000)
Specifies the wait count when switching between the Address and
Chip Enable signal, or the Chip Enable Signal and Write
Enable/Output Enable signal.
*
*
when performing Burst access.
The channel memory size can be set up to 512 MB when
000: Disable
001: 1wait cycle
010: 2 wait cycles
011: 3 wait cycles
Set this bit field to “0” when using it in the Page mode or
9-17
100: 4 wait cycles
101: 5 wait cycles
110: 6 wait cycles
111: 7 wait cycles
Toshiba RISC Processor
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TX4939
9
9