TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 217

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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Manufacturer:
TOSHIBA
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EBC
9.4.7.
Rev. 3.1 November 1, 2005
ACK*/READY
ACK*/READY
SADB [15:0]
SADB [15:0]
Note 1:
Note 2:
Note 3:
AD [21:6]
AD [21:6]
SYSCLK
SYSCLK
SA [5:0]
SA [5:0]
INPUT
INPUT
SWE*
BWE*
SWE*
BWE*
ACE*
ACE*
OE*
OE*
External ACK Mode Access (16-bit Bus)
CE*
CE*
BE*
BE*
Figure 9-30 1-half-word Single Write (0 Wait, SHWT=0, External ACK*, 16-bit Bus)
The TX4939 sets the ACK* signal to High Impedance in the S1 State.
External devices drive the ACK* signal to Low (assert the signal) until the ES1 State.
External devices drive the ACK* signal to High (deassert the signal) in the ES2 State. If an external
device is late in asserting ACK*, then the Wait State is inserted for the amount of time the external
device is late. If a certain condition is met, it is okay for the ACK* signal to be driven to Low for 1 clock
cycle or more. See 9.2.8.4 ACK* Input Timing (External ACK Mode) for more information.
Figure 9-31 1-half-word Single Read (0 Wait, SHWT=0, External ACK*, 16-bit Bus)
F
F
0
0
F
1-Half-Word Single Read (0 Wait, SHWT=0, External ACK*, 16-bit Bus)
1-Half-Word Single Write (0 Wait, SHWT=0, External ACK*, 16-bit Bus)
S1
S1
1
1
ES1
ES1
2
2
F
ES2
ES2
3
3
0
0
0
ES3
S2
4
4
S2
S3
5
5
S3
6
6
7
7
F
F
9-27
8
8
9
9
10
10
11
11
12
12
13
13
F
F
14
14
F
F
Toshiba RISC Processor
15
15
16
16
17
17
18
18
TX4939
19
19
Rev 2.12
Rev 2.12
9
9

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