TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 227

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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NDFMC
10.3. Detailed Operation
10.3.1. Registers
10.3.2. Convention for following explanation
NDFDTR and NDFMCR are the essential registers. Figure 10-2 shows field definition of them.
Table 10-2 and Table 10-3 show Mnemonics used in this section. In addition, following expressions mean writing the
parameter in to corresponding register.
Rev. 3.1 November 1, 2005
Offset Address
0x5000
0x5008
0x5010
0x5018
0x5020
0x5028
NDFDTR
NDFMCR
$NDFMCR = CLE | CE ;
15
15
Mnemonic
NDC_READ1
NDC_READ2
NDC_READ3
NDC_WRITE
NDC_AUTOP
NDC_STATS
NDC_READID
NDC_RESET
Mnemonic
ND_CLE
ND_ALE
ND_CH0
ND_CH1
ND_CH2
ND_CH3
ND_CE
ND_ECCR
ND_ECCE
ND_ECCD
ND_ECCRD
ND_WE
ND_DMA1
ND_DMA2
ND_DMA3
ND_X16B
14
14
13
13
Bit Width
32
32
32
32
32
32
Value
0x00
0x01
0x50
0x80
0x10
0x70
0x90
0xFF
Value
0x0001
0x0002
0x0000
0x0004
0x0008
0x000C
0x0010
0x0060
0x0020
0x0000
0x0040
0x0080
0x0100
0x0200
0x0300
0x0400
DATA [15:8]
12
12
Figure 10-2 Field Definition of Registers NDFDTR and NDFMCR
Table 10-2 Mnemonic Command Parameter for NDFDTR
Register Symbol
NDFDTR
NDFMCR
NDFSR
NDFISR
NDFIMR
NDFSPR
11
11
Explanation
NAND Flash Command READ Data from 0 to 255 byte position
NAND Flash Command READ Data from 256 to 511 byte position.
NAND Flash Command READ Data from the redundant byte
NAND Flash Command WRITE Data from the top of page.
NAND Flash Command Invoke Auto-Program Operation
NAND Flash Command READ Status
NAND Flash Command ID READ operation
NAND Flash Command Initialize NAND
Explanation
Assert CLE
Assert ALE
Select NAND #0
Select NAND #2
Select NAND #3
Select NAND #4
Activate NAND Controller
Reset ECC Circuit
ECC Enable
ECC Disable
READ ECC generated by NDFMC or UPDATE external latch
Activate Write Enable
Activate 128 Byte DMA Transfer
Activate 256 Byte DMA Transfer
Activate 512 Byte DMA Transfer
Set to 16-bit Bus Mode
// Write 0x0011 to register NDFMCR
Table 10-3 Mnemonic Parameter for NDFMCR
X16
10
10
Table 10-1 NDFMC Registers
DMAREQ
9
9
Register Name
NAND Flash Memory Data Transfer Register (R/W)
NAND Flash Memory Mode Control Register (R/W)
NAND Flash Memory Status Register (Read)
NAND Flash Memory Controller Reset (Write)
NAND Flash Memory Interrupt Status Register(RO)
NAND Flash Memory Interrupt Mask Register (R/W)
NAND Flash Memory Strobe Pulse Width Register(R/W)
8
8
10-3
WE
7
7
6
6
ECC
5
5
DATA [7:0]
CE
4
4
3
3
Toshiba RISC Processor
CS[1:0]
2
2
ALE
1
1
CLE
0
0
TX4939
10
10

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