TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 229

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

NDFMC
10.3.4. Initialization and UPDATE
NAND Flash Controller should be initialized after power on and before use. Since six of NAND Controller signal use
external latches, these latch statuses have to be synchronize with corresponding internal registers. This synchronization is
the “UPDATE” operation in this document.
For initialization and UPDATE, three registers, such as NDFSR, NDFDTR, and NDFMCR are used.
Figure 10-2 shows field definition of these registers. Section 10.5.1, 10.5.2, 10.5.3 describe details.
Writing any data to NDFSR register (NAND Flash Memory Status Register =NAND Flash Memory Controller Reset)
initializes entire NAND Flash Controller.
NDFMCR (NAND Flash Mode Control Register) consists of signal control bits and mode control bits. The signal control bits
are WE, CE, CS [1:0], ALE, and CLE, those are transformed to NDRE*, NDWE*, NDCE* NDCS [1:0], ALE, and CLE.
Among these signals, the connection from CE to NDCE* signal is direct but the rests are through external latches. Control
program has to update the logic status of external latches whenever it changes the contents of register. The name of this
operation is UPDATE. Below is an example.
Since this dummy write (to NDFDTR) invokes a real bus transaction on external bus, it has better result than software wait
loop in terms of clock cycle consumed. (Note that the execution period of the software timer might fluctuate depend on the
CPU Cache situation). The duration of this bus transaction consists of pulse width, hold time, and overhead. (where pulse
width and hold time are defined by the register NDFSPR in terms of GBUSCLK period and minimum overhead is 4
GBUSCLK period). Please see corresponding register descriptions.
Following example shows on the fly UPDATE with wait cycle.
Rev. 3.1 November 1, 2005
NDFSR (Low Byte)
NDFDTR (Half Word)
NDFMCR (Half Word)
NDFMC initialize followed by UPDATE Sequence
$NDFSR
$NDFSPR = 0x0106;
$NDFMCR = 0x0000;
$NDFDTR = 0x0000;
On the fly UPDATE
***
$NDFMCR = ND_CE|ND_CH0|ND_CLE;
$NDFDTR = NDC_READ1;
$NDFMCR = ND_CE|ND_CH0|ND_ALE;
$NDFDTR = <Times of necessary>;
$NDFMCR = ND_CE|ND_CH0;
for(i=0;i<4;i++)
***
15
15
BUSY
$NDFDTR = 0x0000;
7
14
14
= 0x0000;
13
13
DMARUN
6
DATA [15:8]
12
12
Figure 10-3 Field Definition of Registers NDFDTR and NDFMCR
11
11
5
X16
10
10
// initialize entire NAND Controller
// Set SPW=6, HOLD=1 (optional)
// Set WE=0, ALE=0, CLE=0 at least. (For simple UPDATE)
// Dummy write to NDFDTR, This invoke NAND bus transaction
// with only ND_LA assertion.
DMAREQ
9
9
4
8
8
10-5
// Assert the ND_CLE* for the Command mode.
// Data Read command.
// ND_ALE* signal
// Set Addresses
// De-assert ALE
// UPDATE and Wait tWB (60ns x 4 = 240ns)
WE
7
7
3
RESERVED
6
6
ECC
5
5
2
DATA [7:0]
CE
4
4
3
3
CS[1:0]
Toshiba RISC Processor
1
2
2
ALE
1
1
0
CLE
0
0
TX4939
10
10