TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 23

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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Index
List of Tables
Rev. 3.1 November 1, 2005
Table 1-1 Major Functional IPs shared by pin multiplexing. ..................................................................................... 1-2
Table 2-1 Periphheral Clock and Reset Control ....................................................................................................... 2-3
Table 3-1 Pin Assignment Table ............................................................................................................................... 3-1
Table 3-2 Power Pin Assignment ............................................................................................................................. 3-3
Table 3-3 GPIO Signal Multiplexing ....................................................................................................................... 3-13
Table 3-4 I2S Signals ............................................................................................................................................. 3-13
Table 3-5 Pin Multiplex for ATA100-0 Channel ....................................................................................................... 3-14
Table 3-6 Function Selecting Map.......................................................................................................................... 3-15
Table 3-7 Pin Multiplex for ATA100-1 Channel ....................................................................................................... 3-15
Table 3-8 Function Selecting Map.......................................................................................................................... 3-16
Table 3-9 Pin Multiplex for Video ports................................................................................................................... 3-16
Table 3-10 ISA Signal Multiplexing......................................................................................................................... 3-17
Table 3-11 PCICLK signal multiplexing .................................................................................................................. 3-17
Table 4-1 Boot Configuration Details........................................................................................................................ 4-2
Table 5-1 Methods for Source Clock Generation ..................................................................................................... 5-4
Table 5-2 Relation between source clock and result frequency ............................................................................... 5-4
Table 5-3 Corresponding Prescaler value for each source clock. ............................................................................ 5-5
Table 5-4 Frequency Error in the Final Clocks ......................................................................................................... 5-6
Table 5-5 mdgen_32_147 Operation........................................................................................................................ 5-7
Table 5-6 Jitter Value in case of 451.584 MHz Source Clock................................................................................... 5-8
Table 5-7 Jitter Value in case of 338.688 MHz Source Clock................................................................................... 5-8
Table 5-8 Audio Clock Control Registers.................................................................................................................. 5-9
Table 5-9 Recommended Values for PLL Parameter ............................................................................................... 5-9
Table 5-10 Bit Field Definitions of MCLKOSC Register.......................................................................................... 5-10
Table 5-11 Parameter FS[1:0] and C2S ................................................................................................................. 5-10
Table 5-12 Bit Field Definitions............................................................................................................................... 5-11
Table 6-1 Internal Registers for DDR SDRAM Mapping Control .............................................................................. 6-3
Table 6-2 DDR Mapping Window Control ................................................................................................................ 6-4
Table 6-3 DDR Mapping Window Control ................................................................................................................ 6-5
Table 6-4 P2G Memory Space (n) PCI Lower Address Register .............................................................................. 6-7
Table 6-5 Corresponding of Memory Space Size and MSS[31:20] Value ................................................................ 6-8
Table 6-6 32-bit Size Access to 64-bit Register (SRAM, EBUSC, PCIC1, PCIC, DMAC0/1) ................................... 6-9
Table 6-7 32-bit Size Access to 64-bit Register (CRYPT, DDR, Config)................................................................... 6-9
Table 6-8 Register Map.......................................................................................................................................... 6-10
Table 6-9 Internal Registers for ATA0..................................................................................................................... 6-11
Table 6-10 Internal Registers for ATA1................................................................................................................... 6-12
Table 6-11 Internal Registers for NAND Controller (NDFMC) ................................................................................ 6-12
Table 6-12 Internal Registers for SRAM Controller (SRAMC) ................................................................................ 6-13
Table 6-13 Internal Registers for Crypto Controller ................................................................................................ 6-13
Table 6-14 Internal Registers for PCI Controller for ETHERC (PCIC1).................................................................. 6-14
Table 6-15 Internal Registers for DDR SDRAM Controller (DDRC) ....................................................................... 6-16
Table 6-16 Internal Registers for External Bus Controller (EBUSC)....................................................................... 6-17
Table 6-17 Internal Registers for Video Port Controller (VPC) ............................................................................... 6-17
Table 6-18 Internal Registers for DMA Controller (DMAC0)................................................................................... 6-18
Table 6-19 Internal Registers for DMA Controller (DMAC1)................................................................................... 6-19
Table 6-20 Internal Registers for PCI Controller (PCIC)......................................................................................... 6-20
Table 6-21 Internal Registers for GBUS to PCI Interface ....................................................................................... 6-21
Table 6-22 Internal Registers for Chip Configuration ............................................................................................. 6-22
Table 6-23 Internal Registers for Timer(s).............................................................................................................. 6-23
Table 6-24 Internal Registers for Serial I/O (Channel 0) ........................................................................................ 6-24
Table 6-25 Internal Registers for Serial I/O (Channel 2) ........................................................................................ 6-24
Table 6-26 Internal Registers for Serial I/O (Channel 1) ........................................................................................ 6-24
Table 6-27 Internal Registers for Serial I/O (Channel 3) ........................................................................................ 6-24
Table 6-28 Internal Registers for Interrupt Controller (IRC).................................................................................... 6-25
Table 6-29 Internal Registers for AC Link............................................................................................................... 6-26
Table 6-30 Internal Registers for Serial Peripheral Interface (SPI) ........................................................................ 6-26
Table 6-31 Internal Registers for I2C Controller..................................................................................................... 6-27
Table 6-32 Internal Registers for I2S Controller ..................................................................................................... 6-27
Table 6-33 Internal Registers for RTC Controller ................................................................................................... 6-27
Table 6-34 Internal Register for CIR Controller ...................................................................................................... 6-27
Table 7-1 Configuration Register Mapping............................................................................................................... 7-2
Table 7-2 Chip Configuration Register ..................................................................................................................... 7-4
Table 7-3 Chip Revision ID Register ........................................................................................................................ 7-7
xix
Toshiba RISC Processor
TX4939

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