TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 230

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

NDFMC
10.3.5. Write Sequence (8-bit Bus, Program Mode)
Rev. 3.1 November 1, 2005
Write Sequence
////////////////////////////////////////////
// Write Sequence (512-Byte)
////////////////////////////////////////////
$NDFMCR = ND_CH0;
$NDFDTR = 0x0000;
$NDFMCR = ND_ECCR|ND_CH0;
$NDFMCR = ND_CE|ND_CH0|ND_CLE;
$NDFDTR = NDC_WRITE;
$NDFMCR = ND_CE|ND_CH0|ND_ALE;
$NDFDTR = 0x0FF & ( A );
$NDFDTR = 0x0FF & ( A >> 9);
$NDFDTR = 0x0FF & ( A >> 17);
$NDFDTR = 0x01
$NDFMCR = ND_WE|ND_ECCEN|ND_CE|ND_CH0;
for(i=0;i<512;i++)
{
}
////////////////////////////////////////////
// Read ECC data from FDFMC
////////////////////////////////////////////
$NDFMCR = ND_ECCRD|ND_CE|ND_CH0;
for(I = 0;I < 6;i++)
{
}
////////////////////////////////////////////
// Write 16-bytes Redundant Data
////////////////////////////////////////////
$NDFMCR= ND_WE|ND_ECCD|ND_CE|ND_CH0;
for(I = 0;I < 16;i++)
{
}
////////////////////////////////////////////
// Execute Auto-Program
////////////////////////////////////////////
$NDFMCR = ND_ECCD|ND_CE|ND_CH0|ND_CLE;
$NDFDTR = NDC_AUTOP;
$NDFMCR = ND_CE|ND_CH0;
$NDFDTR = 0x0000;
////////////////////////////////////////////
// Wait until “BUSY” goes off
////////////////////////////////////////////
while ((0x01 & $NDFISR) == 1){}
////////////////////////////////////////////
// Read status
////////////////////////////////////////////
$NDFMCR = ND_CE|ND_CH0|ND_CLE;
$NDFDTR = NDC_STATS;
$NDFMCR = ND_CE|ND_CH0 ;
$NDFDTR = 0x0000;
Status
$NDFMCR = 0x0000;
$NDFDTR = 0x0000;
////////////////////////////////////////////
// Repeat this process for other pages
////////////////////////////////////////////
$NDFDTR = DATA[i];
RDR[i] = $NDFDTR;
$NDFDTR = RDATA [i];
= $NDFDTR;
& ( A >> 25);
//
//
//
//
//
//
//
10-6
// Select CH#0 and set WE=0 for prepare UPDATE
// UPDATE the Latch
// Initialize ECC circuit
// Assert the ND_CLE* for the Command mode.
// Write 0x80 (Data Write command).
// Assert ND_ALE* for the Address mode.
// Set A[7:0]
// Set A[16:9]
// Set A[24:17]
// (A[25] if necessary)
// Set ECC enable and enter Data mode.
// Set 512-Byte data in order.
// Calculated ECC Data Read mode.
// Activate NDFMC on CH#0, and initialize
// the ECC data of NDFMC.
// Enter the Command mode.
// Write 0x10 (Page Program command).
// De-assert ND_WE and ND_CLE*.
// UPDATE (CLE)
// Assert the ND_CLE* for Command Mode.
// Write 0x70 (Read Status command).
// De-assert the ND_CLE*
// UPDATE CLE and short wait
// Read status value
// Release NAND
// UPDATE
Toshiba RISC Processor
TX4939
10
10