TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 231

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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NDFMC
10.3.6. Read Sequence (8-bit Bus, Program / DMA Mode)
Rev. 3.1 November 1, 2005
Read Sequence (8-bit Bus, Program / DMA Mode)
////////////////////////////////////////////
// Read Sequence
////////////////////////////////////////////
$NDFMCR = ND_CH0;
$NDFDTR = 0x0000;
$NDFMCR = ND_ECCR|ND_CH0;
$NDFMCR = ND_CE|ND_CH0|ND_CLE;
////////////////////////////////////////////
// Read Command and Address setting
////////////////////////////////////////////
$NDFDTR = NDC_READ1;
$NDFMCR = ND_CE|ND_CH0|ND_ALE;
$NDFDTR = 0x0FF & ( A );
$NDFDTR = 0x0FF & ( A >> 9);
$NDFDTR = 0x0FF & ( A >> 17);
$NDFDTR = 0x001 & ( A >> 25);
$NDFMCR = ND_CE|ND_CH0;
$NDFDTR = 0x0000;
for(i=0;i<4;i++)
while( (0x01 & $NDFSR) == 1){}
$NDFMCR = ND_ECCE|ND_CE|ND_CH0;
////////////////////////////////////////////
// Read 512 byte data
////////////////////////////////////////////
if(DMAMODE)
{
}
else
{
}
////////////////////////////////////////////
// Get the ECC data calculated.
////////////////////////////////////////////
$NDFMCR = ND_CE|ND_CH0;
for(i=0;i<16;i++)
{
}
////////////////////////////////////////////
// Read ECC calculated by NDFMC
////////////////////////////////////////////
$NDFMCR = ND_ECCR|ND_CE|ND_CH0;
for(i=0;i<6;i++)
{
}
$NDFMCR = 0x0000;
$NDFDTR = 0x0000;
////////////////////////////////////////////
// Compare the ECC data.
// If the data do not match, invoke the
// necessary error process.
////////////////////////////////////////////
$NDFDTR = 0x0000;
$NDFMCR = ND_DMA3|ND_ECCE|ND_CE|ND_CH0;
for(i = 0;i < 512;i++)
{
}
RDATA[i] = $NDFDTR;
RECC[i] = $NDFDTR;
DATA[i] = $NDFDTR;
// Program mode
//
//
//
//
//
//
//
//
10-7
// Select CH#0 and set WE=0 for prepare UPDATE
// UPDATE the Latch
// Initialize ECC circuit
// Assert Command Latch Enable
// Data Read command.
// ND_ALE* signal
// Set A[7:0]
// Set A[16:9]
// Set A[24:17]
// (A[25] if necessary) in order.
// Prepare de-assert ALE
// UPDATE (ALE)
// Wait tWB (60ns x 4 = 240ns)
// Wait until Data Ready
// Set ECC Enable
// Invoke DMA Operation for 512 bytes.
// Set 0x10, Enter Data mode w/o ECC
// Set 0x50, and enter the ECC Data Read mode.
// Release NAND
// UPDATE
Toshiba RISC Processor
TX4939
10
10

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