TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 233

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

NDFMC
10.4. ECC and DMA Operation
10.4.1. ECC Generation
ECC data consists of line and column parity. The 512 bytes data is treated as two sets of 256 x 8 bit memory array. Each
memory array can contain one bit error as correctable and two bit error detectable. Following table describes complete
formula to generate ECC data. LPR00 = LPR[0] = EXOR(0XXXXXXX0,XXX) means an odd-parity with all data bit which
address A8, A0 is 0 and the rest of addresses are 0 and 1.
For detail explanation of this ECC structure, please refer http://www.ssfdc.or.jp and,
the document of "SmartMedia ECC Reference Manual Ver 2.1".
Rev. 3.1 November 1, 2005
ECC
LPR00
LPR01
LPR02
LPR03
LPR04
LPR05
LPR06
LPR07
LPR08
LPR09
LPR10
LPR11
LPR12
LPR13
LPR14
LPR15
CPR00
CPR01
CPR02
CPR03
CPR04
CPR05
LPR16
LPR17
LPR18
LPR19
LPR20
LPR21
LPR22
LPR23
LPR24
LPR25
LPR26
LPR27
LPR28
LPR29
LPR30
LPR31
CPR06
CPR07
CPR08
CPR09
CPR10
CPR11
= EXOR (
= EXOR (
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A8 A7 A6 A5 A4 A3 A2 A1 A0
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Toshiba RISC Processor
COMMENT
TX4939
10
10