TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 234

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

NDFMC
10.4.2. ECC Data Format
ECC generates LPR [31:0] and CPR [11:0] (totally 44-bit data). Use a program to check ECC for errors and correct any
errors that occur.
You can read from the NDFDTR Register the ECC data calculated by NDFMC by setting the NDFMCR to either 0xD0 (Write
mode) or 0x50 (Read mode). The ECC data you can read is 6-Byte data. Read NDFDTR six times. Data is read in the
following order.
As an example, this ECC data will be stuffed in the part of 16-byte redundant data space of NAND Flash. This redundant
memory cell is 16-bytes. Those are numbered from D512 to D527. Figure 10-4 shows the location of this ECC. Please
note that this structure is purely example and actual system might use its own structure.
10.4.3. DMA Operation
Refer to Section 14.3.7 in DMA Controller.
This DMA Operation uses DMA0 Channel 3. The burst size is 8-bytes (Double Word), from NDFMC to memory is
supported. Before using DMA0 Operation DMA0 channel 3 should be properly set as follows.
Once DMA transfer is requested, NDFMC generates DATA READ sequence to NAND memory continuously and is filling
the FIFO (16-bytes). When 8-bytes data are filled, the controller assert DMAREQ signal to DMAC. Same time, controller
release the external bus once and connect NAND memory again if there are rooms in the FIFO. If FIFO has no room, the
controller disconnects NAND and waits until FIFO get a room.
Rev. 3.1 November 1, 2005
LPR[23:16]
D512
D520
First data:
Second data:
Third data:
Fourth data:
Fifth data:
Sixth data:
DMA Request Polarity
DMA Acknowledge Polarity
Request Detection
Transfer Size
Transfer Direction
Transfer Address Mode
I/O DMA Transfer Mode
Pin Config in shared DMA
Note: Destination Address (in memory) should be Double-Word aligned.
Function Select Information Field
LPR[31:24]
D513
D521
LPR[7:0]
LPR[15:8]
CPR[5:0], 2’b11
LPR[23:16]
LPR[31:24]
CPR[11:6], 2’b11
CPR[11:6]+11
Figure 10-4 ECC Position in NAND Data Space.
D514
D522
Low Active
Low Active
Level Detection
8 Byte
I/O to Memory
Single
External
Set to NDFMC
D515
D523
Fixed
0x00
10-10
Invalid Data Flag
D516
D524
Fixed
0x00
DM0CCR3.REQPOL = 0
DM0CCR3.ACKPOL = 0
DM0CCR3.EGREQ = 0
DM0CCR3.XFSZ = 011b
DM0CCR3.MEMIO = 0
DM0CCR3.SNGAD = 1
DM0CCR3.EXTRQ = 1
PCFG.DMASEL3 = 1’b0
LPR[7:0]
D517
Fixed
D525
0xFF
Toshiba RISC Processor
LPR[15:8]
D518
Fixed
D526
0x00
CPR[5:0]+11
D519
Fixed
D527
0x00
TX4939
10
10