TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 239

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

NDFMC
10.5.3. NAND Flash Memory Status Register (NDFSR)
A write to this register will reset entire NAND Flash Controller (NDFMC) and registers.
A read will return hardware status describes as follow.
10.5.4. NAND Flash Memory Interrupt Status Register (NDFISR)
Rev. 3.1 November 1, 2005
Bits
31 : 8
7
6
Bits
31 : 8
7 : 2
1
0
BUSY
R/O
7
-
7
-
Mnemonic
⎯
BUSY
DMARUN
Mnemonic
⎯
-
DMADONE
RDY
DMARUN
R/O
6
-
6
-
Figure 10-12 NAND Flash Memory Interrupt Status Register (NDFISR)
Table 10-7 NAND Flash Memory Interrupt StatusRegister (NDFISR)
Figure 10-11 NAND Flash Memory Status Register (NDFSR)
Field Name
Reserved
BUSY
DMARUN
Field Name
Reserved
Reserved
DMADONE
Ready
Table 10-6 NAND Flash Memory Status Register (NDFSR)
5
5
RESERVED
Description
⎯
BUSY (Default: Undefined)
Indicates the status of NAND flash memory.
0: Ready
1: Busy
DMA Status
Indicates the status of DMA channel working on NDFMC.
0: STOPPED
1: RUNNING
Description
⎯
DMA Status
A ‘1’ indicates all the requested byte transfer which is specified in NDFMCR register
have been transferred to FIFO.
Write:
0: Don’t care
1: Clear to “0”
Ready (Default: 0)
When the MRDY bit of the NDFIMR Register is "1", this bit is set to "1" when the
ND_RB* signal changes from Low to High. Write "1" to clear this bit to "0".
Read:
0: No change
1: ND_RB* signal changed from the Busy state to the Ready state.
Write:
0: Don’t care
1: Clear to "0".
4
4
10-15
3
3
RESERVED
2
2
DMADONE
R/O
Toshiba RISC Processor
1
1
0
0x5010
RDY
R/W
0
0
0
0x5018
TX4939
: Default
: Default
: Type
: Type
10
10