TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 242

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

NDFMC
10.6. Timing diagram
10.6.1. Initialization Sequence
Required initialization Steps after power on:
Step 1 : Write to NDFSR. This will reset entire NDFMC registers.
Step 2 : Write to NDFSPR with the proper value of Write Pulse Width and Hold Time
Step 3 : Write any data to NDFDTR. This will generate ND_LA and synchronize the external latch status with internal value.
LEGEND for above and following timing chart
Rev. 3.1 November 1, 2005
GBUSCLK
NDCS[1:0]
BUSACK
BUSREQ
SA [5:0]
ND_LA
NDWE*
Idle
NDALE
NDCLE
Wn
BG
SU
HD
NDRE*
Hn
0
GBUS Idle state
Bus Get cycle for GBUS
Inherit set up cycle from SA[5:0] and SADB[15:0] to ND_LA, NDRE*, and NDWE*
PW state corresponds to the programmed pulse width (SPW). This will be from [PW1] to
PW15]. NDWE* signal will be asserted exactly only this states, where NDRE* assertion
will be kept until next H1 states.
HOLD state corresponds to the programmed hold time (HOLD). This will be from [H1] to
[H15]. NDRE* signal assertion will be kept at H1 state.
Inherit hold cycle from ND_LA de-assertion to SA [5:0] release. Since SADB [15:0] will
be released at the same time with SA [5:0], for the hold time from NDRE* or NDWE*
de-assertion to SADB [15:0] release has one additional cycle.
Initialization and Update of External LATCH Device (SPW=6, HOLD=2)
Idle
BG
SU
3
Internal signal for External BUS Interface.
Internal signal for External BUS Interface.
Figure 10-15 Initialization and Update Sequence
W1
4
W2
5
W3
6
Designated Value
60 ns
W4
7
10-18
W5
8
W6
0
9
H1
10
H2
11
HD
12
Timing Values in this chart are based
GBUSCLK = 200 MHz (T
SPW=6, and HOLD=2
13
14
Toshiba RISC Processor
15
Possible Next Cycle
16
Possible Next Cycle
CYCLE
0
17
= 5ns),
18
TX4939
19
Rev 2.14
10
10