TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 255

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

Video Port
12.3. Operations
Video Port Controller has two modes of operations.
There are two errors condition that the VPC controller will check.
Internal to the VPC controller, there is one 16x64 bit FIFO per port. This FIFO is shared for both transmit and capture
mode.
12.3.1. Video Port DMA Controller
The Video Port DMA controller has the following features:
The VPC’s DMA engine has one channel to transfer data between memory and the VPC engine. There are four tasks for
the DMA.
There is one buffer per port inside VPC engine, this buffer shared for both transmit mode and receive mode.
Each video port has its own descriptor list. VPC’s DMA engine processes the descriptor lists in round robin fashion.
Rev. 3.1 November 1, 2005
Output mode (transmit), in this mode the TX4939 is the master. VPC controller will begin to fetch the data from the
memory and transfer it out to the video port.
Input mode (capture), in this mode the TX4939 is the slave. VPC controller will begin to capture the data on the
video port and transfer these data into the memory accordingly.
Overflow error. When VPC is in capture mode, the overflow error occurs when there is an overflow in the capture
FIFO. This condition is only happen when internal data bus can not transfer data out of the FIFO fast enough
compare to the input data rate.
Underflow error. When VPC is in transmit mode, the underflow error occurs when there is an underflow in the
transmit FIFO. This condition is only happen when the internal data bus can transfer data into the FIFO fast
enough compare to the output data rate.
Supports register access
Supports master mode for G-bus protocol (single and burst transfer)
Supports chain and link list DMA protocol
Supports un-alignment byte data transfer for Transmit mode only. For Capture mode, all data are align to double
word boundary (64-bit)
To get a descriptor
To update the status in a descriptor when transfer complete
To transfer received data from FIFO (receive mode) to memory
To transfer transmit data from memory to FIFO (transmit mode).
12-3
Toshiba RISC Processor
TX4939
12
12