TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 256

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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Video Port
12.3.2. 8-bit Parallel port
VPC supports two video formats. The two formats are ITU.Bt.656 and EN50083-9’s Synchronous Parallel Interface. For
the EN50083-9 format, data length and packet length are programmable from 128 bytes to 8192 bytes.
In TX4939, VDCLKIN clock is the source clock for VPC controller.
12.3.2.1. ITU.Bt656 Interface
This is a 8-bit ITU.Bt.656 (CCIR656) interface.
12.3.2.2. Synchronous Parallel Interface
The data to be tramsmitted are MPEG-2 Transport Packets with 188, 204 bytes or user defined. In the case of the 204 byte
packet format packets may contains a 16 bytes “empty space”, a VDVLD Signal serves to identify these dummy bytes.
VDPSN flag is to identify the beginning of a packet. The data are synchronized to the VDCLK.
Rev. 3.1 November 1, 2005
VDCLK
VD[7:0]
VDCLK
VD[7:0]
VDPSN
VD[7:0]
VD[7:0]
VDCLK
VDPSN
VDCLK
VDPSN
-
-
VDVLD
VDCLKIN connect to VDCLKO directly.
Internal controller uses VDCLKIN as clock source.
Figure 12-5 Transmission format with RS-coded packets (204 Bytes, VDVLD = 1)
187 sync
203 sync
187
Cb0
Figure 12-3 Transmission format with 188 Byte packets (VDVLD = 1)
Figure 12-4
(188 data bytes and 16 dummy bytes – dummy byte = 8’h00)
1
1
sync
Figure 12-2 ITU.BT656 (CCIR656) Digital Video Timing
2
2
Y0
1
Transmission format with 204 Byte packets
Cr0
2
12-4
Y1
Cb1
187
1
Y2
2
3
186
Toshiba RISC Processor
Cr1
187
202 203 sync 1
Y3
15
sync
16 sync 1
Cb2
TX4939
1
12
12

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