TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 263

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

Video Port
12.3.6.2. ControlA (CtrlA)
Note: Port configuration is selected by TX4939’s configuration setting.
* Video Port Mode is only applicable to video port 1 and video port 2. This bit is programmable for video port 3 but since
video port 3 is input port only, software must program this bit to 1. Programming 0 will cause undefined behavioral.
Rev. 3.1 November 1, 2005
Bit(s)
63:10
9
8
7
6
5:4
3
2
1
0
Field
–
VDPSN
PBUSY
DCINT
UOINT
PDINT
Vdvldp
Vdmode
VDFOR
ENVPC
R/W
RO
R/W
RO
RO
RO
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
01
0
0
0
0
Table 12-3 ControlA Register (CtrlA)
Description
Reserved
VDPSN bit width selection in serial output mode.
Port Busy Status
This bit is useful for the transmit case in which DMA completion interrupt can be
generated way ahead of the port transmission completion. System should check
this status bit before issuing new operation to the same port. Otherwise, the new
operation may terminate an ongoing transmission operation prematurely.
NOTE: Default value is only valid when the video port’s corresponding video
clock is supplied while a reset is applied.
DMA Completion Interrupt
This bit will be clear after read cycle.
Underflow/Overflow Error Interrupt
Overflow error only occurs when VPC is in capture mode.
Underflow error only occurs when VPC is in transmit mode.
Programmable DMA Completion Interrupt
00: Interrupt for every descriptor at completion of transfer.
01: Interrupt only when Next Descriptor pointer = Null at completion of transfer.
10: Interrupt only when Next Descriptor pointer = Null at completion of transfer.
11: Disable DMA Completion Interrupt
VDVLD polarity select
Video Port Mode*
Video Format
Start VPC Engine
When write “1” to this bit, VPC engine will begin to operate.
0: No interrupt
1: Transfer complete
12-11
0: VDPSN is 8-bit wide
1: VDPSN is 1-bit wide
1: Port is busy
0: Port is idle
0 : No error
1 : Underflow/Overflow error
0: Active high (default)
1: Active low
0: output mode (Master) – transmit (default)
1: input mode (Slave) – receive
0: ITU.Bt.656 (default)
1: MPEG-2 Transport Stream
0: Idle
1: Start
CtrlA1
CtrlA2
CtrlA3
Toshiba RISC Processor
0xA008
0xA028
0xA048
TX4939
12
12