TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 280

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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TMR
13.6.2. Timer Interrupt Status Register n (TMTISRn)
Rev. 3.1 November 1, 2005
Default
Default
Bit
31:4
3
2
1
Name
Name
Type:
Type:
TMTISR0 (0xF004), TMTISR1 (0xF104), TMTISR2 (0xF204),
TMTISR3 (0xFD04), TMTISR4 (0xFE04), TMTISR5 (0xFF04)
Mnemonic
TWIS
TPIBS
TPIAS
31
15
30
14
Field Name
Reserved
Watchdog Timer
Status
Pulse Generator
TMCPRB Status
Pulse Generator
TMCPRA Status
29
13
28
12
Figure 13-8 Timer Interrupt Status Register
Table 13-4 Timer Interrupt Status Register
27
11
Description
Watchdog Timer TMCPRA Match Status (Default: 0)
(This bit is Reserved other than TMTISR2 Register.)
When in the Watchdog Timer mode, this bit is set when the counter value
matches Compare Register A2 (TMCPRA2).
This bit is cleared by writing a “0” to it.
During Read
0: Did not match the Compare Register
1: Matched the Compare Register
During Write
0: Negate interrupt
1: Invalid
Pulse Generator TMCPRB Match Status (Default: 0)
(This bit is Reserved in case of TMTISR2 Register.)
When in the Pulse Generator mode, this bit is set when the counter value
matches Compare Register Bn (TMCPRBn).
This bit is cleared by writing a “0” to it.
During Read
0: Did not match the Compare Register
1: Matched the Compare Register
During Write
0: Clear
1: Invalid
Pulse Generator TMCPRA Match Status (Default: 0)
(This bit is Reserved in case of TMTISR2 Register.)
When in the Pulse Generator mode, this bit is set when the counter value
matches Compare Register A n (TMCPRAn).
This bit is cleared by writing a “0” to it.
During Read
0: Did not match the Compare Register
1: Matched the Compare Register
During Write
0: Clear
1: Invalid
26
10
Reserved
25
9
13-12
RESERVED
24
8
23
7
22
6
21
5
20
4
Toshiba RISC Processor
RW0C RW0C RW0C RW0C
TWIS TPIBS TPIAS
19
3
0
18
2
0
17
1
0
R/W
R/W0C
R/W0C
R/W0C
TX4939
TIIS
16
0
0
13
13

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