TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 284

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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TMR
13.6.5. Interval Timer Mode Register n (TMITMRn)
Rev. 3.1 November 1, 2005
Default
Default
Bit
31:16
15
14:1
0
Name
Name
Type:
Type:
TMITMR0 (0xF010), TMITMR1 (0xF110), TMITMR2 (0xF210),
TMITMR3 (0xFD10), TMITMR4 (0xFE10), TMITMR5 (0xFF10)
Mnemonic
TIIE
TZCE
R/W
TIIE
31
15
0
30
14
Field Name
Reserved
Interval Timer
Interrupt Enable
Reserved
Interval Timer
Clear Enable
29
13
28
12
Figure 13-11 Interval Timer Mode Register
Table 13-7 Interval Timer Mode Register
27
11
Description
Timer Interval Interrupt Enable (Default: 0)
Sets Interval Timer TMCPRA Interrupt Enable/Disable.
0: Disable (mask)
1: Enable
Interval Timer Zero Clear Enable (Default: 0)
This bit specifies whether or not to clear the counter to “0” after the count
value matches Compare Register A. Count stops at this value if it is not
cleared.
0: Do not clear
1: Clear
26
10
25
9
13-16
RESERVED
RESERVED
24
8
23
7
22
6
21
5
20
4
Toshiba RISC Processor
19
3
18
2
17
1
R/W
R/W
R/W
TX4939
TZCE
R/W
16
0
0
13
13

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