TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 297

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

DMA
14.3.7.2. Burst Transfer During Single Address Transfer
According to the SDRAM Controller and External Bus Controller specifications, the DMA Controller cannot perform Burst
transfer that spans across 32-double word boundaries. Consequently, if the address that starts DMA transfer is not a
multiple of the transfer setting size (DMCCRn.XFSZ) (is not aligned), transfer cannot be performed by any of the transfer
sizes that were specified by a Burst transfer. Therefore, the DMA Controller executes multiple Burst transactions of a
transfer size smaller than the specified transfer size. This division method changes according to the seting of the Transfer
Size Mode bit (DMCCRn.USEXFSZ) of the DMA Channel Control Register.
Figure 14-3 shows the Single Address Burst transfer status when the lower 8 bits of the Transfer Start address are 0xA8
and the transfer setting size (DMCCRn.XFSZ) is set to 4 double words.
Panel (a) of this figure shows the situation when the Transfer Size Mode bit (DMCCRn.USEXFSZ) is “0”. In this case, first a
three-double word transfer is performed up to the address aligned to the transfer setting size. Then, four-double word
transfer specified by the transfer setting size is repeated. This setting is normally used.
On the other hand, panel (b) shows when the Transfer Size Mode bit (DMCCRn.USEXFSWZ) is “1”. In this case, transfer is
repeated according to the transfer setting size. Three-double word transfer and one-double word transfer is only performed
consecutively without releasing bus ownership when transfer spans across a 32-double word boundary.
Rev. 3.1 November 1, 2005
a0
a8
b0
b8
d0
d8
e0
e8
00
08
10
18
20
28
30
38
40
48
50
58
60
c0
c8
f0
f8
63
(a) DMCCRn.USEXFSZ
0
Figure 14-3 Non-aligned Single Address Burst Transfer
3 Double Words
4 Double Words
4 Double Words
4 Double Words
4 Double Words
4 Double Words
DMCCRn.XFER = 4
32 Double Word Boundary
=
“0”
14-9
(b) DMCCRn.USEXFSZ
a0
a8
b0
b8
c0
c8
d0
d8
e0
e8
00
08
10
18
20
28
30
38
40
48
50
58
60
f0
f8
63
0
Toshiba RISC Processor
4 Double Words
4 Double Words
(3 + 1) Double Words
4 Double Words
4 Double Words
4 Double Words
DMCCRn.XFER = 4
=
“1”
TX4939
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