TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 298

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

DMA
14.3.8. Dual Address Transfer
This section explains the register settings for Dual Address transfer (DMCCRn.SNGAD = 0). This applies to the following
DMA transfer modes.
14.3.8.1. Channel Register Settings During Dual Address Transfer
Table 14-3 shows restrictions of the Channel Register settings during Dual Address transfer. If these restrictions are not
met, then a Configuration Error is detected, the Configuration Error bit (CFERR) of the DMA Channel Status Register
(DMCSRn) is set, and DMA transfer is not performed.
If the setting of the DMA Source Address Increment Register (DMSAIRn) is negative and the transfer setting size is 8
bytes or larger, then a value will be set in the DMA Source Address Register (DMSARn) that reflects as follows.
If the setting of the DMA Source Address Increment Register (DMSAIRn) is negative and the transfer size is 2 bytes or
larger, set the DMA Source Address Register (DMSARn) as follows:
Likewise, if the setting of the DMA Destination Address Increment Register (DMDAIRn) is negative and the transfer size
is 2 bytes or larger, set the DMA Destination Address Register (DMDARn) as follows:
Example:
follows below.
Rev. 3.1 November 1, 2005
1 Byte
2 Bytes
4 Bytes
8 Bytes,
4 / 8
(DMMCR.FIFUM[n]=
0)
4 / 8 Double Words
(DMMCR.FIFUM[n]=
1)
16 Double Words
32 Double Words
Transfer Setting Size
(DMCCRn.XFSZ)
‡:
Double Wods
□ External I/O (Dual Address) transfer
□ Internal I/O DMA transfer
□ Memory-Memory Copy transfer
□ If the transfer size is 2 bytes, set the DMSARn with the low-order 1 bit complemented.
□ If the transfer size is 4 bytes, set the DMSARn with the low-order 2 bits complemented.
□ If the transfer size is 8 bytes or larger, set the DMSARn with the low-order 3 bits complemented.
□ If the transfer size is 2 bytes, set the DMDARn with the low-order 1 bit complemented.
□ If the transfer size is 4 bytes, set the DMDARn with the low-order 2 bits complemented.
□ If the transfer size is 8 bytes or larger, set the DMDARn with the low-order 3 bits complemented.
□ DMSAIRn setting is “0” or greater: 0x0_0001_0000
□ DMSAIRn setting is a negative value: 0x0_0001_0007
8, 0, or -8 can be specified when the Destination Burst Inhibit bit (DMCCRn.DBINH) is set.
Table 14-3 Channel Register Setting Restrictions During Dual Address Transfer
When the transfer address is 0x0_0001_0000, the DMA Source Address Register (DMSARn) is as
Cannot be set (Configuration Error)
Cannot be set (Configuration Error)
setting is 0
DMSAIRn
or greater
000
000
*00
**0
***
***
⎯
DMSARn[2:0]
setting is a
DMSAIRn
negative
value
111
111
*00
**0
***
***
⎯
setting is 0
or greater
DMDAIRn
000
000
*00
**0
***
***
⎯
DMDARn[2:0]
14-10
setting is a
DMDAIRn
negative
value
111
111
*11
**1
***
***
⎯
DMSAIRn
8/0/-8
000
*00
**0
***
-8
8
DMDAIRn
8/-8 ‡
000
*00
**0
***
-8
8
Toshiba RISC Processor
DMCNTRn
000
000
*00
**0
***
***
REVBYTE
DMCCRn
TX4939
0/1
0/1
0
0
0
0
0
14
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