TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 300

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

Toshiba RISC Processor
DMA
TX4939
On the other hand, panel (b) show when the address offset is not equivalent. In this case, first only data up to the
address that is aligned with the transfer setting size is read to the on-chip FIFO. Then, data is written up to the address
that is aligned with the transfer setting size as long as data remains in the on-chip FIFO. Efficiency decreases since the
transfer size is divided. Also, since data may remain in the on-chip FIFO, Burst transfer of a Dual Address that uses the
on-chip FIFO simultaneously with another channel cannot be performed.
Using the Burst Inhibit bit makes it possible to mix Burst transfer with 8-Double-Word Single transfer. This in turn makes it
possible to perform Burst access only for memory access during DMA transfer with external I/O devices that cannot
perform Burst transfer.
When the Source Burst Inhibit bit (DMCCRn.SBINH) is set, data read from the Source Address to the on-chip FIFO is
divided into multiple 8-byte Single Read transfers, then transfer is executed.
When the Destination Burst Inhibit bit (DMCCRn.DBINH) is set, data written from the FIFO to the Destination Address is
divided into multiple 8-byte Single Write transfers, then transfer is executed.
14.3.8.3. Double Word Byte Swapping
When the Reverse Byte bit (REVBYTE) of the DMA Channel Configuration Register (DMCCRn) is set, read double word
data is written after byte swapping is performed. For example, if the read data is “0x01234567_89ABCDEF”, then the
data “0xEFCDAB89_67452301” is written.
The Reverse Byte bit can only be set when the REVBYTE column of Table 14-3 is set so “0/1” is indicated.
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Rev. 3.1 November 1, 2005
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