TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 302

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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DMA
14.3.9. DMA Transfer
The sequence of DMA transfer that uses only the DMA Channel Register is as follows below.
Rev. 3.1 November 1, 2005
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
Select DMA request signal
When performing external I/O or internal I/O DMA, set the DMA Request Select field
(PCFG.DMASEL) of the Pin Configuration Register.
Set the Master Enable bit
Set the Master Enable bit (DMMCR.MSTEN) of the DMA Master Control Register.
Set the Address Register and Count Register
Set the five following register values.
Set Chain Address Register
Set “0” to the DMA Chain Address Register (DMCHARn).
Clear the DMA Channel Status Register (DMCSRn)
Clear when status from the previous DMA transfer remains.
Set the DMA Channel Control Register (DMCCRn)
Initiate DMA transfer
DMA transfer is started by setting the Transfer Active bit (XFACT) of the DMA Channel Control
Register.
Signal completion
When DMA data transfer ends normally, the Normal Transfer Complete bit (NTRNFC) of the
DMA Channel Status Register (DMCSRn) is set. An interrupt is signalled if the Transfer
Complete Interrupt Enable bit (INTENT) of the DMA Channel Control Register (DMCCRn) is
set.
If an error is detected during DMA transfer, the error cause is recorded in the lower four bits of
the DMA Channel Status Register and the transfer is interrupted. If the Error Interrupt Enable
bit (INTENE) of the DMA Channel Control Register is set, then the interrupt is signaled.
□ DMA Source Address Register (DMSARn)
□ DMA Destination Address Register (DMDARn)
□ DMA Count Register (DMCNTRn)
□ DMA Source Address Increment Register (DMSAIRn)
□ DMA Destination Address Increment Register (DMDAIRn)
14-14
Toshiba RISC Processor
TX4939
14
14

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