TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 304

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

DMA
The sequence of Chain DMA transfer is as follows below.
Rev. 3.1 November 1, 2005
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Select DMA request signal
When performing external I/O or internal I/O DMA, set the DMA Request Select field (PCFG.DMASEL)
of the Pin Configuration Register.
Set the Master Enable bit
Set the Master Enable bit (DMMCR.MSTEN) of the DMA Master Control Register.
Structure of the DMA command Descriptor chain
Construct the DMA Command Descriptor Chain in memory.
Set the Count Register
Set “0” to the DMA Count Register (DMCNTRn) .
Sets the DMA Source Address Increment Register (DMSAIRn) and DMA destination Address Increment
Register (MMDAIRn).
Clear the DMA Channel Status Register (DMCSRn)
Clear the status of the previous DMA transfer.
Set the DMA Channel Control Register (DMCCRn).
Initiate DMA transfer
Setting the address of the DMA Command Descriptor at the beginning of the chain list in the DMA
Chain Address Register (DMCHARn) automatically initiates DMA transfer. First, the value stored in each
field of the DMA Command descriptor at the beginning of the Chain List is read to each corresponding
DMA Channel register (Chain transfer), then DMA transfer is performed according to the read value.
When a value other than “0” is stored in the DMA Chain Address Register (DMCHARn), data of the size
stored in the DMA Count Register (DMCNTRn) is completely transferred, then the DMA Command
Descriptor value of the memory address specified by the DMA Chain Address Register is read.
In addition, if the Chain Address field value read the Descriptor 0, the DMA Chain Address Register
value is not updated. All previous values (Data Command Descriptor Addresses with the value “0” in the
Chain Address field when the values were read) are held.
0 Value judgement is performed when the lower 32 bits of the DMA Chain Address Register are
rewritten. If the value is not “0” at this time, DMA transfer is automatically initiated. Therefore, please
write to the upper 32 bits first when writing to the DMA Chain Address Register using 32-bit Store
instructions.
Signal completion
Set the Normal Chain End bit (NCHNC) of the DMA Channel Status Register (DMCSRn) when DMA
data transfer of all Descriptor Chains is complete. An interrupt is signalled if the Chain End Interrupt
Enable bit (INTENC) of the DMA Channel Control Register (DMCCRn) is set at this time.
In addition, the Normal Transfer End bit (NTRNFC) of the DMA Channel Status Register (DMCSRn) is
set each time DMA data transfer specified by each DMA Command Descriptor ends normally.
interrupt is signalled if the Transfer End Interrupt Enable bit (INTENT) of the DMA Channel Control
Register (DMCCRn) is set at this time.
If an error is detected during DMA transfer, the error cause is recorded in the lower four bits of the DMA
Channel Status register and transfer is interrupted. An interrupt is signalled if the Error Interrupt Enable
bit (INTENE) of the DMA Channel Control Register is set.
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Toshiba RISC Processor
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