TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 312

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

DMA
14.4.2. DMA Channel Control Register (DM0CCRn, DM1CCRn)
Offset address:
Rev. 3.1 November 1, 2005
Bit
63:32
29
28
27
Default
Default
Default
Default
Name
Name
Name
Name
Type
Type
Type
Type
Mnemonic
IMMCHN
USEXFSZ
LE
STLTIME/INTRQD
63
47
31
15
Reserved
DMAC0 0xB030 (ch. 0) / 0xB070 (ch. 1) / 0xB0B0 (ch. 2) / 0xB0F0 (ch. 3)
DMAC1 0xB830 (ch. 0) / 0xB870 (ch.1 ) / 0xB8B0 (ch. 2) / 0xB8F0 (ch. 3)
R/W
000
62
46
30
14
IMMC
Field Name
Reserved
Immediate Chain Immediate Chain (Default: 0)
Transfer Set Size
Mode
Little Endian
R/W
HN
61
45
29
13
0
INTEN
USEX
FSZ
R/W
R/W
60
44
28
12
E
0
0
Figure 14-10 DMA Channel Control Register
INTEN
Table 14-8 DMA Channel Control Register
R/W
R/W
LE
59
43
27
⎯
11
C
0
Description
Always set this bit to “1”.
1: means that DMAC will automatically enter chain mode from the last
transfer so the bus is held and there is no penalty to reacquire the bus.
0: means that the DMAC gives up the bus between the last transfer on a
channel and the chain operation for that channel.
Use Transfer Set Size (Default: 0)
Selects the DMA channel operation mode during Burst DMA transfer. Refer
to “14.3.7.2” and “14.3.8.2 Burst Transfer During Dual Address Transfer” for
more information.
1:
DMCCRn.XFSZ for each bus operation. Since alignment to the boundary of
the DMCCRn.XFSZ in the address is not forced when in this mode, transfers
that exceed 32-double-word boundaries are divided into two operations.
0:
in DMSARn and DMDARn (only during Dual Address transfer) can be
aligned to the boundary of the size set in DMCCRn.XFSZ, then transfers data
according to that size.
Note:
only when both the contents of the DMSARn and the DMDARn are on
doubleword boundaries and the contents of the DMCNTRn is a multiple of
eight bytes.
Little Endian (Default: value that is the opposite of the G-Bus Endian
(CCFG.ENDIAN)
This bit sets the Endian of the channel. Please use the default value as is.
1: Channel operates in the Little Endian mode
0: Channel operates in the Big Endian mode
DBINH SBINH
INTEN
R/W
R/W
58
42
26
10
T
0
0
The DMA Controller always transfers the amount of data set in
The DMA Controller calculates the transfer size so the address set
In Dual Address Transfer mode, programming this bit to 0 is valid
CHNE
R/W
57
41
25
N
R
0
9
0
14-24
CHRS
XFAC
RESERVED
RESERVED
R/W
R/W
56
40
24
T
T
1
8
0
RVBY
R/W
TE
55
39
23
Reserved
0
7
ACKP
R/W
OL
54
38
22
0
6
REQP
SMPC
R/W
R/W
HN
53
37
21
L
0
5
0
EGRE
R/W
52
36
20
Q
0
4
Toshiba RISC Processor
CHDN
XFSZ
R/W
R/W
000
51
35
19
0
3
50
34
18
2
DNCTL
R/W
00
MEMI
R/W
49
33
17
O
1
0
R/W
⎯
R/W
R/W
R/W
TX4939
SNGA
EXTR
R/W
R/W
48
32
16
Q
D
0
0
0
14
14