TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 314

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

DMA
Rev. 3.1 November 1, 2005
Bit
16
15:13
12
11
10
Mnemonic
EXTRQ
STLTIME /
INTRQD
INTENE
INTENC
INTENT
Field Name
External Request External Request (Default: 0)
Transfer Stall
Detection
Interval/Internal
Request Delay
Error Interrupt
Enable
Chain End
Interrupt Enable
Transfer End
Interrupt Enable
Table 14-8 DMA Channel Control Register
Description
Sets the Request Transfer mode.
1: I/O DMA transfer mode
This bit is used by the External I/O DMA Transfer mode and the Internal I/O
DMA Transfer mode. A channel requests internal bus ownership when the I/O
device asserts the DMA request signal.
0: Memory Transfer mode
This bit is used by the Memory-Memory Copy Transfer mode and the
Memory Fill Transfer mode. A channel requests internal bus ownership when
the value of DMCSRn.WAITC becomes “0”.
When in the I/O DMA Transfer mode (DMCCRn.EXTRQ is “1”)
Stalled Transfer Detect Time (Default: 000)
Sets the detection interval for a lack of bus ownership. If this channel n
releases bus ownership then the interval it does not have ownership exceeds
the clock count set by this field, then DMCSRn.STLXFER is set to “1”. Refer
to “0
Transfer Stall Detection Function” for more information.
000: Does not detect stalled transfers.
001: Sets 960 (15 × 64) clocks as the detection interval
010: Sets 4032 (63 × 64) clocks as the detection interval
011: Sets 16320 (255 × 64) clocks as the detection interval
100: Sets 65472 (1023 × 64) clocks as the detection interval
101: Sets 262080 (4095 × 64) clocks as the detection interval
110: Sets 1048512 (16383 × 64) clocks as the detection interval
111: Sets 4194240 (65535 × 64) clocks as the detection interval
When in the Memory Transfer mode (DMCCRn.EXTRQ is “0”)
Internal Request Delay (Default: 000)
Sets the delay time from when bus ownership is released to the next bus
ownership request. Bus ownership is released, the set delay time elapses,
then a bus ownership request is generated from the channel.
000: Always requests bus ownership when this channel is active.
001: Set 16 clocks as the delay time
010: Set 32 clocks as the delay time
011: Set 64 clocks as the delay time
100: Set 128 clocks as the delay time
101: Set 256 clocks as the delay time
110: Set 512 clocks as the delay time
111: Set 1024 clocks as the delay time
Interrupt Enable on Error (Default: 0)
Enables interrupts when the Error End bit (DMCSRn.ABCHC) or the Transfer
Stall Detection bit (DMCSRn.STLXFER) is set.
1: Generates interrupts.
0: Does not generate interrupts.
Interrupt Enable on Chain Done (Default: 0)
This bit enables interrupts when the Chain End bit (DMCSRn.NCHNC) is set.
1: Generate interrupts.
0: Do not generate interrupts.
Interrupt Enable on Transfer Done (Default: 0)
This bit enables interrupts when the Transfer End bit (DMCSRn.NTRNFC) is
set.
1: Generate interrupts.
0: Do not generate interrupts.
(Bus ownership is released after bus operation ends)
14-26
Toshiba RISC Processor
R/W
R/W
R/W
R/W
R/W
R/W
TX4939
14
14