TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 316

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

DMA
14.4.3. DMA Channel Status Register (DM0CSRn, DM1CSRn))
Offset Address:
Rev. 3.1 November 1, 2005
Bit
63:32
31:16
15:11
10
9
Default
Default
Default
Default
Name
Name
Name
Name
Type
Type
Type
Type
Mnemonic
WAITC
CHNEN
STLXFER
63
47
31
15
DMAC0 0xB038 (ch. 0) / 0xB078 (ch. 1) / 0xB0B8 (ch. 2) / 0xB0F8 (ch. 3)
DMAC1 0xB838 (ch. 0) / 0xB878 (ch. 1) / 0xB8B8 (ch. 2) / 0xB8F8 (ch. 3)
62
46
30
14
Reserved
Field Name
Reserved
Wait Counter
Reserved
Chain Enable
Transfer Stall
Detect
61
45
29
13
60
44
28
12
Figure 14-11 DMA Channel Status Register
Table 14-9 DMA Channel Status Register
59
43
27
11
Description
Wait Counter (Default: 0x0000)
This is a diagnostic function.
• I/O DMA transfer mode (DMCCRn.EXTRQ = “1”)
This counter is decremented by 1 at each 64 G-Bus cycles. After channel n
releases bus ownership, this counter sets the default (the value that is the
detection interval clock cycle count set by the Transfer Stall Detection Interval
field (DMCCRn.STLTIME) divided by 64). The Transfer Stall Detect bit
(DMCSRn.STLXFER) is set when the interval during which bus ownership is
not held reaches the set clock cycle. The counter is reset to the default and
stops counting. Clearing the Transfer Stall Detect bit (DMCSRn.STLXFER)
resumes the count and starts stall detection.
• Memory transfer mode (DMCCRn.EXTRQ = “0”)
This counter is decremented by 1 at each G-Bus cycle. After bus ownership is
released, the counter is set to the delay clock cycle count set by the Internal
Request Delay field (DMCCRn.INTRQD). When the counter reaches “0” the
count stops and channel n requests bus ownership.
Chain Enable (Default: 0)
This value is a copy of the Chain Enable bit (CHNEN) of the DMA Channel
Control Register (DMCCRn).
Stalled Transfer Detect (Default: 0)
This bit indicates whether the interval during which bus ownership is not held
exceeds the value set by the Transfer Stall Detect Interval field
(DMCCRn.STLTIME) after bus ownership is released when in the I/O DMA
transfer mode.
1:
exceeds the DMCCRn.STLTIME setting.
0:
exceed the setting since this bit was last cleared.
CHNE
58
42
26
10
N
R
0
Indicates that the interval during which bus ownership was not held
The interval during which bus ownership was not held did not
STLXF
R/W1C
ER
57
41
25
9
0
14-28
XFAC
RESERVED
RESERVED
56
40
24
T
R
8
0
0x0000
WAITC
R
ABCH
55
39
23
C
R
7
0
R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C
NCHN
54
38
22
C
6
0
NTRN
FC
53
37
21
5
0
EXTD
52
36
20
N
4
0
Toshiba RISC Processor
CFER
51
35
19
R
3
0
CHER
50
34
18
R
2
0
DESE
RR
49
33
17
1
0
R/W
⎯
R
⎯
R
R/W1C
TX4939
SORE
RR
48
32
16
0
0
14
14