TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 317

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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DMA
Rev. 3.1 November 1, 2005
Bit
8
7
6
5
4
3
2
1
0
Mnemonic
XFACT
ABCHC
NCHNC
NTRNFC
EXTDN
CFERR
CHERR
DESERR
SORERR
Field Name
Transfer Active
Error Complete
Chain Complete
Transfer
Complete
External DONE
Asserted
Configuration
Error
Chain Bus Error
Destination Error
Source Bus Error
Table 14-9 DMA Channel Status Register
Description
Transfer Active (Default: 0)
This value is a copy of the Transfer Active bit (XFACT) of the DMA Channel
Control Register (DMCCRn).
Error Completion (Default: 0)
This bit indicates whether an error occurred during DMA transfer. This bit
indicates the logical sum of the four error bits (CFERR, CHERR, DESERR,
SORERR) in DMCSRn[3:0].
1: DMA transfer ends due to an error.
0: No error occurred since this bit was last cleared.
Normal Chain Completion (Default: 0)
When performing chain DMA transfer, This bit indicates whether all DMA data
transfers in the DMA Descriptor chain are complete.
1:
normally. Or, DMA transfer that did not use a DMA Descriptor chain ended
normally.
0:
cleared.
Normal Transfer Completion (Default: 0)
This bit indicates whether DMA transfer ended according to the current DMA
Channel Register setting.
1: DMA transfer ended normally.
0: DMA transfer has not ended since this bit was last cleared.
External Done Asserted (Default: 0)
This bit indicates whether an external I/O device asserted the DMADONE*
signal. When the DMADONE* signal is set to bidirectional, this bit is also set
when the TX4939 asserts the DMADONE* signal.
1: DMADONE* signal was asserted.
0: DMADONE* signal was not asserted.
Configuration Error (Default: 0)
Indicates whether an illegal register setting was made.
1: There was a configuration error.
0: There was no configuration error.
Chain Bus Error (Default: 0)
This bit indicates whether a bus error occurred while reading a DMA
Command Descriptor.
1: Bus error occurred.
0: No bus error occurred.
Destination Bus Error (Default: 0)
This bit indicates whether a bus error occurred during a destination bus Write
operation (a Write to a set DMDARn address).
1: Bus error occurred.
0: No bus error occurred.
Source Bus Error (Default: 0)
This bit indicates whether a bus error occurred during either a source bus
Read or Write operation (A Read or Write to a set DMSARn address).
1: Bus error occurred.
0: No bus error occurred.
All DMA data transfers in the DMA Descriptor chain ended
DMA transfer has not ended normally since this bit was last
14-29
Toshiba RISC Processor
R/W
R
R
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
TX4939
14
14

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