TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 318

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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DMA
14.4.4. DMA Source Address Register (DM0SARn, DM1SARn)
Offset Address:
Rev. 3.1 November 1, 2005
Default
Default
Default
Default
Name
Name
Name
Name
Bits
63:36
35:0
Type
Type
Type
Type
Mnemonic
SADDR
63
47
31
15
DMAC0 0xB008 (ch. 0) / 0xB048 (ch. 1) / 0xB088 (ch. 2) / 0xB0C8 (ch. 3)
DMAC1 0xB808 (ch. 0) / 0xB848 (ch. 1) / 0xB888 (ch. 2) / 0xB8C8 (ch. 3)
62
46
30
14
Field Name
Reserved
Source Address
61
45
29
13
60
44
28
12
Figure 14-12 DMA Source Address Register
Table 14-10 DMA Source Address Register
59
43
27
11
Description
Source Address (Default: Undefined)
This field sets the physical address of the transfer source during Dual
Address transfer. This field sets the physical address of memory access
during Single Address transfer. This field is used for either Memory-to-I/O or
I/O-to-Memory transfers.
Refer to “14.3.7.1” and “14.3.8.1 Channel Register Settings During Dual
Address Transfer” for more information.
During Burst transfer, the value changes once for each bus operation only by
the size that was transferred. During Single transfer, the value only changes
by the value specified by the DMA Source Address Increment Register
(DMSAIRn).
RESERVED
58
42
26
10
57
41
25
9
14-30
SADDR[31:16]
SADDR[15:0]
RESERVED
56
40
24
8
R/W
R/W
55
39
23
7
54
38
22
6
53
37
21
5
52
36
20
4
Toshiba RISC Processor
51
35
19
3
SADDR[35:32]
50
34
18
2
R/W
49
33
17
1
R/W
R/W
TX4939
48
32
16
0
14
14

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