TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 323

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

DMA
14.4.9. DMA Count Register (DM0CNTRn, DM1CNTRn)
Offset Address:
Rev. 3.1 November 1, 2005
Default
Default
Default
Default
Name
Name
Name
Name
Bit
63:26
25:0
Type
Type
Type
Type
Mnemonic
DMCNTR
63
47
31
15
DMAC0 0xB018 (ch. 0) / 0xB058 (ch. 1) / 0xB098 (ch. 2) / 0xB0D8 (ch. 3)
DMAC1 0xB818 (ch. 0) / 0xB858 (ch. 1) / 0xB898 (ch. 2) / 0xB8D8 (ch. 3)
62
46
30
14
Field Name
Reserved
Count
RESERVED
61
45
29
13
60
44
28
12
59
43
27
11
Figure 14-17 DMA Count Register
Description
Count Register (Default: undefined)
This register sets the byte count that is transferred by the DMA Channel
Register setting. The value is a 26-bit unsigned data that is decremented only
by the size of the data transferred during a single bus operation.
Refer to “14.3.8.1 Channel Register Settings During Dual Address Transfer”
for more information.
Table 14-15 DMA Count Register
58
42
26
10
57
41
25
9
14-35
DMCNTR[15:0]
RESERVED
RESERVED
56
40
24
8
R/W
⎯
55
39
23
7
54
38
22
6
DMCNTR[25:0]
53
37
21
5
R/W
⎯
52
36
20
4
Toshiba RISC Processor
51
35
19
3
50
34
18
2
49
33
17
1
R/W
⎯
R/W
TX4939
48
32
16
0
14
14