TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 344

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

DDR
15.7.2.3. DDR Mapping Window #n (n=0, 1, 2, 3)
DRWIN00, DRWIN01, DRWIN02, and DRWIN03 control DDR Mapping condition independently.
When the system receives an effective physical address, (EPA), it checks following condition for enabled window(s).
Then, if it is true, Corresponding DDR channel will be accessed with following DDR_EFFECTIVE_ADDRESS.
Rev. 3.1 November 1, 2005
Bit
63:48
47:42
41:32
31:26
25:16
15:2
1:0
R/W
R/O
63
35
47
31
15
0
0
IF ( ( EPA <= DRWINUP_ADRS ) && ( EPA >= DRWINLO_ADRS) )
DDR_EFFECTIVE_ADDRESS = EPA – DRWINLO_ADRS + DRWINOF_ADRS
Mnemonic
DRWINLO
DRWINUP
DRWINUP
⎯
DRWINOF
⎯
CS [1:0]
COPY of DRWINLO [35:30]
R/W
R/O
62
34
46
30
14
0
0
DRWINLO [35:30]
RESERVED
R/W
R/O
61
33
45
29
13
0
0
R/W
R/O
Field Name
DRWINLO [35:20]
DRWINUP [35:30]
DRWINLO [29:20]
RESERVED
DRWINOF [29:20]
RESERVED
Chip Select [1:0]
60
32
44
28
12
0
0
R/W
R/O
59
31
43
27
11
0
0
R/W
R/O
58
30
42
26
10
0
0
Figure 15-9 DDR Mapping Window Control
Table 15-2 DDR Mapping Window Control
RESERVED
Description
Define the lower address of window #n in physical address.
DRWINLO_ADRS = { DRWINUP [35:20], 20'HF_FFFF }
This register is the copy of DRWINLO [35:30]
Define the upper address of window #n in physical address.
DRWINUP _ADRS = { DRWINUP [35:20], 20'H0_0000 }
⎯
Define the offset address of the target DDR memory space.
DRWINOF _ADRS = { DRWINOF [29:20], 20'H0_0000 }
⎯
Define corresponding DDR channel number with CS
CS[1:0] = 2'b00 Channel 0 (CS0)
CS[1:0] = 2'b01 Channel 0 (CS0)
CS[1:0] = 2'b10 Channel 1 (CS1)
CS[1:0] = 2'b11 Channel 1 (CS1)
NOTE: CS setting should be consistent with DDR_CTRL15 setting.
R/W
R/W
R/W
57
29
41
25
0
0
0
9
R/W
R/W
R/W
56
28
40
24
0
0
0
8
R/W
R/W
R/W
15-14
55
27
39
23
0
0
0
7
R/W
R/W
R/W
54
26
38
22
0
0
0
6
DRWINLO [29:20]
DRWINUP [29:20]
DRWINOF [29:20]
R/W
R/W
R/W
53
25
37
21
0
0
0
5
R/W
R/W
R/W
52
24
36
20
4
0
0
0
R/W
R/W
R/W
51
23
35
19
0
0
0
3
R/W
R/W
R/W
50
22
34
18
0
0
0
2
Toshiba RISC Processor
R/W
R/W
R/W
49
21
33
17
0
0
0
1
CS [1:0]
R/W
0
R/W
R/W
R/W
48
32
16
20
0
0
0
0
Initial
Value
0
0
0
⎯
0
⎯
0
: Default
: Default
: Default
: Default
: R/W
: R/W
: R/W
: R/W
TX4939
R/W
R/W
R/O
R/W
⎯
R/W
⎯
R/W
15
15