TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 345

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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DDR
15.8. DDR SDRAM Controller
The DDR SDRAM controller is configured with the following features:
The DDR SDRAM controller has the following advanced features:
15.8.1. Initialization protocol
The controller is designed such that it requires the following sequence for correct operation after all power to the ASIC and
to the memory devices are stable. The controller does not have any circuitry that controls the activation of power and
ground to the system. Once the power is stable to the memory devices and the ASIC, the following procedure is required
to initialize the controller. The controller will initialize the memory devices automatically once this procedure is completed.
The controller will generate an interrupt (INT_STATUS[2] in DDR_CTL_01 register) to the CPU once the DRAM initialization
is complete and the internal DCC is locked.
Rev. 3.1 November 1, 2005
Maximum Byte Request = 256 bytes
Register Data Width = 16 bits
Half cas latency support
Register DLL Value – DLL value is stored in a user-readable register
Drive data/dqs when idle – allows the user (under register control) to have the controller drive the data and dqs
signals during the times in which the controller is idle
Support Registered DIMMs
Self Refresh (register controllable)
Masked Writes
DLL Bypass Option
Command Queue Depth = 4
Write Queue Depth = 1 (no FIFO)
Read Queue Depth = 1 (no FIFO)
Supported clock frequencies from 100 MHz to 200 MHz
Wrap command support for critical first word access
Auto Precharge (register controllable)
Memory Data Width = 32 bits
Maximum Chip Selects = 2 (supports 2 physical banks)
DQ:DQS Ratio = 8 (every data byte has one DQS signal)
Maximum Columns Supported = 12 (supports x8 x16 DDR SDRAM)
Maximum Address Pins = 14 (supports 1Gbit DDR SDRAM)
Address Order = CS, Row, Bank
Fully pipelined command, read, and write data interface to the controller
Advanced bank look-ahead features for high memory throughput
Programmable register interface to control memory device parameters and protocols including auto precharge
Full initialization of memory upon reset of the controller
Built in adjustable Delay Compensation Circuitry (DCC or DLL) for reliable data send and capture timing
Assert the reset pin. All programmable registers will be set to zero when the reset pin is asserted.
De-assert the reset pin synchronously to the controller clock.
Reset DDR deskew PLL by writing 0 and then 3 to the DDRDSKW field of the DLL De-Skew Control Register (see
chapter on Configuration Registers).
Issue write register commands to program all the registers to configure the DRAM protocols and the settings for
the DCC in the controller. The Start register must be kept at 0 during this initialization step.
Register values to be used for a specific memory part can be obtained by running the register_gen.tcl tickle script
with the corresponding memory part’s SOMA file as input.
Write a 1 into the Start register. Once this register is written with a 1, the controller will go through the initialization
sequence specified by the parameters written into the registers of the controller.
15-15
Toshiba RISC Processor
TX4939
15
15

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