TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 346

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

DDR
15.8.2. Supported DDR SDRAM Configurations
This controller supports the SDRAM configurations listed below in Table 15-3.
15.8.3. Delay Line Tuning
Write Datapath
Essentially, for the write datapath the parameters need to be adjusted according the "flight times" while maintaining the 90
degree phase between the write data and the write DQS:
For the write datapath, there are two registers that control the capture of data at the DRAM interface:
Getting the DQS signal to arrive at a certain point in a clock cycle at the DRAM is a function of the generation of the DQS
signal and the physical delays in transmitting this signal from one point to another.
t_flight = t_io_cell + t_driver + t_board.
The write data sent along with the DQS strobe must be aligned such that the strobe rises and falls within the valid region of
the data with maximum setup and hold characteristics. This translates into the write data being clocked 1/4 cycle (90
degree) before the rising edge of the DQS strobe.
The values for TC300C_WR_DQS_SHIFT and TC300C_DQS_OUT_SHIFT are determined by the min and max physical
delays of t_io_cell, t_driver, and t_board.
The goal is to have the DQS signal arrive at the DRAMs as close to the rising edge of the clock as possible. Once the
typical delay values are calculated for these delays, the parameter values are chosen such that the clk_wr signal
arrives at the IO cell 1 cycle minus this value.
Rev. 3.1 November 1, 2005
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TC300C_WR_DQS_SHIFT[8:0] - Controls the delay for the clk_wr signal which is used to clock the write data such
that the phase between the write data and write_dqs is always 90 degrees. The unit of this parameter is degree.
For example, to delay by half of a clock cycle(equivalent to a 180 degree phase shift) TC300C_WR_DQS_SHIFT
should be programmed to 180(0xB4). This is fine tunable post silicon to accommodate for DQ routing.
TC300C_dqs_out_shift[8:0] - Controls the delay for the DQS signal for write. Again, the unit of the parameter is
degree.
128 Mbit
256 Mbit
512 Mbit
64Mbit
DDR SDRAM Configuration
1 Gbit
4-bank
4-bank
4-bank
4-bank
4-bank
Table 15-3 Supported DDR SDRAM Configration
16M x 16
1M x 16
1M x 32
2M x 16
2M x 32
4M x 16
8M x 16
16M x 8
32M x 8
4M x 8
8M x 8
Row Address (bit)
15-16
12
12
12
12
12
13
13
13
13
14
14
Column Address (bit)
Toshiba RISC Processor
10
10
10
11
10
11
8
8
9
9
9
TX4939
15
15