TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 347

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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DDR
Recommended Delay Settings
Example setting of parameters
Below is an example of the calculations necessary to choose the correct value of
TC300C_WR_DQS_SHIFT and TC300C_DQS_OUT_SHIFT:
• Clock frequency = 200MHz (5ns)
• t_io_cell(typ) = 100 ps (+/- 20%)
• t_driver(typ) = 1500 ps (+/- 30%)
• t_board(typ) = 500ps (+/- 10%)
• tdqss = +/- 0.25clk
Typical delay is 2100ps or 0.42clk.
This means that adding an additional 1/2 clock would place the DQS signal within 0.08clk of the rising edge.
So, setting TC300C_DQS_OUT_SHIFT to:
TC300C_DQS_OUT_SHIFT = 180
would accomplish this delay.
To maintain the 1/4 clk phase difference between the write data and write DQS, TC300C_WR_DQS_SHIFT shoud be set to:
TC300C_WR_DQS_SHIFT = 180 - 90 = 90
The min and max variation of the arrival time is +/- 520ps.
This is 0.10 of a clock cycle. This means that the DQS signal would arrive 0.82 to 1.02 of a clock cycle around the clock edge.
This is within the 0.75 to 1.25 specification of the DRAM.
Read Datapath
For the read path, there are 4 delay parameters that need to be programmed:
1.) DDR_CTL_39, TC300C_DLL_DQS_DELAY_0 for byte 0 or bit[7:0]
2.) DDR_CTL_40, TC300C_DLL_DQS_DELAY_1 for byte 1 or bit[15:8]
3.) DDR_CTL_41, TC300C_DLL_DQS_DELAY_2 for byte 2 or bit[23:16]
4.) DDR_CTL_42, TC300C_DLL_DQS_DELAY_3 for byte 3 or bit[31:24]
These parameters are best calculated by software.
First the software should write a 32-bit data to a memory location.
Then the software would form a loop, to sweep the delay from 0 to 360 degree while attempting
to read each byte. The optimal parameter for each byte is then calcuated as follow:
TC300C_DLL_DQS_DELAY_x = MIN_DELAY + ((MAX_DELAY - MIN_DELAY) / 2)
where
MIN_DELAY = the smallest delay value in which the byte being read is successful
MAX_DELAY = the biggest delay value in which the byte being read is successful.
Rev. 3.1 November 1, 2005
much less than ¼ cycle
close to ¼ cycle
close to ½ cycle
t_flight
3/4 clk (270 degree)
1/2 clk (180 degree)
1/4 clk (90 degree)
clk_wr delay
15-17
3/4 clk (270 degree)
1/2 clk (180 degree)
1 clk (360 degree)
Toshiba RISC Processor
DQS delay
TX4939
15
15

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