TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 349

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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DDR
15.10. Registers
Note: Reserve bits will return 0s when read.
DDR_CTL_00 = 0x8000
DDR_CTL_01 = 0x8008
DDR_CTL_02 = 0x8010
DDR_CTL_03 = 0x8018
Rev. 3.1 November 1, 2005
Name
-
-
-
-
Name
INT_STATUS
-
INT_ACK
-
Name
INT_MASK
-
OUT_OF_RANGE_LENGTH
Name
OUT_OF_RANGE_TYPE
-
START
-
Bits
5:00
7:6
13:08
15:14
Bits
3:0
7:4
10:8
15:11
Bits
3:0
7:3
15:8
Bits
2:0
7:3
8:8
15:9
Default
-
-
-
-
Default
0x0
-
0x0
-
Default
0x0
-
0x00
Default
0x0
-
0x0
-
Range
-
-
-
-
Range
0x0-0xf
-
0x0-0x7
-
Range
0x0-0x7
-
0x0-0xff
Range
0x0-0x7
-
0x0-0x1
-
15-19
Description
Reserved
Reserved
Reserved
Reserved
Description
Status of interrupt features in the controller.
Status of all possible interrupts generated by the controller. The
MSB of this register is the OR of all the lower bits. The Int_status
bits correspond to these interrupts.
0 = Single out of range address detected
1 = Multiple out of range address detected
2 = DRAM initialization complete
3 = Logical OR of all lower bits
READONLY
Reserved
Clear mask of INT_STATUS register.
This register controls clearing the Int_status register. If any of these
bits are set to a one when writing this register, the corresponding bit
in the Int_status register will be set to 0. Any bits written width a 0
will not alter the bit in the Int_status register.
WRITEONLY
Reserved
Description
Mask for controller_int signals from the INT_STATUS register.
The mask applied to the outputs Int_status register that are logically
ORed and reflected to the controller_int pin on the ASIC interface.
Reserved
Length of command that caused Out of Range interrupt.
The user length for an out of range request to the memory devices.
READONLY
Description
Type of command that caused Out of Range interrupt.
READONLY
Reserved
Start bit to control command processing in the controller
Start register. With this register set to 0, the controller will not issue
any commands to the DRAMs or respond to any pin activity except
for reading and writing registers. Once this register is set to 1 the
controller will then respond to inputs from the ASIC.
Reserved
Toshiba RISC Processor
TX4939
15
15

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