TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 352

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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DDR
DDR_CTL_12 = 0x8060
DDR_CTL_13 = 0x8068
DDR_CTL_14 = 0x8070
Rev. 3.1 November 1, 2005
Name
WRITEINTERP
-
AREFRESH
-
Name
NO_CMD_INIT
-
-
Name
TDLL
TWTR
-
Bits
0:0
7:1
8:8
15:9
Bits
0:0
7:1
15:8
Bits
7:0
10:8
15:11
Default
0x0
-
0x0
-
Default
0x0
-
-
Default
0x00
0x0
-
Range
0x0-0x1
-
0x0-0x1
-
Range
0x0-0x1
-
-
Range
0x0-0xff
0x0-0x7
-
15-22
Description
Enable DRAM feature that allows controller to interrupt write bursts
to the DRAMs.
Read interrupt write parameter. When enabled the controller is able
to interrupt a write burst with a read command. Some memory
device do not allow this functionality.
0 = The device does not support read commands interrupting write
commands.
1 = The device does support read commands interrupting write
commands.
Reserved
Execute an autorefresh command immediately or at the next DRAM
burst boundary.
When this register is written with a “1”, and auto precharge command
will be issued to the DRAM devices. If there are any open banks,
the controller will automatically close these banks before issuing the
auto refresh command.
This register will always read back “0”.
WRITEONLY
Reserved
Description
Enable disabling DRAM commands until TDLL has expired during
initialization.
0 = Issue only REF and PRE commands during DLL initialization of
the DRAMs
1 = Do not issue any type command during DLL initialization of the
DRAMs
Reserved
Reserved
Description
DRAM TDLL parameter in cycles.
Dll lock time for DDR SDRAM in cycles
DRAM TWTR parameter in cycles.
The number of cycles needed to switch from a write to a read
operation dictated by the DDR SDRAM specification.
Reserved
Toshiba RISC Processor
TX4939
15
15

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